Resets (RESETS) – Offset 204 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Resets (RESETS) – Offset 204

Bit Range	Default	Access	Field Name and Description
31:3	0h	RO	Reserved (Reserved0) Reserved
2	0h	RW	Reset DMA (reset_dma) Reset the dma controller 0 = IP is in reset (Reset Asserted) 1 = IP is NOT at reset (Reset Released)
1:0	0h	RW	Reset Controller (reset_ip) UART Host Controller reset. Used to reset the UART Host Controller by SW control. All UART Configuration State and Operational State will be forced to the Default state. There is no timing requirement (SW can assert and de-assert in back to back transactions) This reset does NOT impact the LPSS cluster level settings by BIOS, the PCI configuration header information, DMA channel configuration and interrupt assignment/mapping/etc. Driver should re-initialize registers related to Driver context following an UART host controller reset. 00 = UART Host Controller is in reset (Reset Asserted) 01 = Reserved 10 = Reserved 11 = UART Host Controller is NOT at reset (Reset Released)

Bit Range

Default

Access

Field Name and Description

31:3

Reserved (Reserved0)

Reserved

Reset DMA (reset_dma)

Reset the dma controller
0 = IP is in reset (Reset Asserted)
1 = IP is NOT at reset (Reset Released)

1:0

Reset Controller (reset_ip)

UART Host Controller reset.
Used to reset the UART Host Controller by SW control. All UART Configuration State and Operational State will be forced to the Default state.
There is no timing requirement (SW can assert and de-assert in back to back transactions)
This reset does NOT impact the LPSS cluster level settings by BIOS, the PCI configuration header information, DMA channel configuration and interrupt assignment/mapping/etc.
Driver should re-initialize registers related to Driver context following an UART host controller reset.
00 = UART Host Controller is in reset (Reset Asserted)
01 = Reserved
10 = Reserved
11 = UART Host Controller is NOT at reset (Reset Released)

Active LTR (ACTIVELTR_VALUE)

Clock Configuration (CLOCKS) Active LTR (ACTIVELTR_VALUE)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Resets (RESETS) – Offset 204