Root Control (RCTL) – Offset 5c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Root Control (RCTL) – Offset 5c

This is the Root Control registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
15:5	0h	RO	Reserved (RSVD_M) Reserved.
4	0h	RW	CRS Software Visibility Enable (CRSSVE) This bit, when set, enables the Root Port to return Configuration Retry Status (CRS) Completion status to software. 1: Enable software to received a CRS status. This allows software to make the decision to re-issue the configuration request or move on and re-issue the request at a later time. 0: Disable software from receiving a CRS response. The PCIe will wait and re-issue the configuration request until it receives a response other than CRS without notifying software.
3	0h	RW	PME Interrupt Enable (PIE) When set, enables interrupt generation when RSTS.PS is in a set state (either due to a 0 to 1 transition, or due to this bit being set with RSTS.PS already set).
2	0h	RW	System Error on Fatal Error Enable (SFE) When set, an SERR will be generated if a fatal error is reported by any of the devices in the hierarchy of this root port, including fatal errors in this root port. This register is not dependant on CMD.SEE being set.
1	0h	RW	System Error on Non-Fatal Error Enable (SNE) When set, an SERR will be generated if a non-fatal error is reported by any of the devices in the hierarchy of this root port, including non-fatal errors in this root port. This register is not dependant on CMD.SEE being set.
0	0h	RW	System Error on Correctable Error Enable (SCE) When set, an SERR will be generated if a correctable error is reported by any of the devices in the hierarchy of this root port, including correctable errors in this root port. This register is not dependant on CMD.SEE being set.

Root Capabilities (ROOTCAP)

Slot Status (SLSTS) Root Capabilities (ROOTCAP)