SATA Dynamic Clock Gating Enable (PTM4) – Offset 8c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

SATA Dynamic Clock Gating Enable (PTM4) – Offset 8c

Bit Range	Default	Access	Field Name and Description
31:24	0h	RO	RSVD0 (RSVD0) Reserved
23	0h	RW	SATA Port7 PCLK Dynamic clock gating enable (S7PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 7. Note: This register is only applicable to project(s) that have port 7 physically.
22	0h	RW	SATA Port6 PCLK Dynamic clock gating enable (S6PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 6. Note: This register is only applicable to project(s) that have port 6 physically.
21	0h	RW	SATA Port5 PCLK Dynamic clock gating enable (S5PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 5. Note: This register is only applicable to project(s) that have port 5 physically.
20	0h	RW	SATA Port4 PCLK Dynamic clock gating enable (S4PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 4. Note: This register is only applicable to project(s) that have port 4 physically.
19	0h	RW	SATA Port3 PCLK Dynamic clock gating enable (S3PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 3. Note: This register is only applicable to project(s) that have port 3 physically.
18	0h	RW	SATA Port2 PCLK Dynamic clock gating enable (S2PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 2. Note: This register is only applicable to project(s) that have port 2 physically.
17	0h	RW	SATA Port1 PCLK Dynamic clock gating enable (S1PCLKDCGE) Refer to S0PCLKDCGE description. This is for port 1. Note: This register is only applicable to project(s) that have port 1 physically.
16	0h	RW	SATA Port0 PCLK Dynamic clock gating enable (S0PCLKDCGE) 0 indicates SATA Port0 Dynamic clock gating of PCLK is disabled. 1 indicates SATA Port0 Dynamic clock gating of PCLK is enabled.
15:8	0h	RO	RSVD1 (RSVD1) Reserved
7	0h	RW	SATA Port7 Backbone Clock Dynamic clock gating enable (S7DCGE) Refer to S0DCGE for description. This is for port 7. Note: This bit is only applicable to project(s) that have port 7 physically.
6	0h	RW	SATA Port6 Backbone Clock Dynamic clock gating enable (S6DCGE) Refer to S0DCGE for description. This is for port 6. Note: This bit is only applicable to project(s) that have port 6 physically.
5	0h	RW	SATA Port5 Backbone Clock Dynamic clock gating enable (S5DCGE) Refer to S0DCGE for description. This is for port 5. Note: This bit is only applicable to project(s) that have port 5 physically.
4	0h	RW	SATA Port4 Backbone Clock Dynamic clock gating enable (S4DCGE) Refer to S0DCGE for description. This is for port 4. Note: This bit is only applicable to project(s) that have port 4 physically.
3	0h	RW	SATA Port3 Backbone Clock Dynamic clock gating enable (S3DCGE) Refer to S0DCGE for description. This is for port 3. Note: This bit is only applicable to project(s) that have port 3 physically.
2	0h	RW	SATA Port2 Backbone Clock Dynamic clock gating enable (S2DCGE) Refer to S0DCGE for description. This is for port 2. Note: This bit is only applicable to project(s) that have port 2 physically.
1	0h	RW	SATA Port1 Backbone Clock Dynamic clock gating enable (S1DCGE) Refer to S0DCGE for description. This is for port 1. Note: This bit is only applicable to project(s) that have port 1 physically.
0	0h	RW	SATA Port0 Backbone Clock Dynamic clock gating enable (S0DCGE) 0 indicates SATA Port0 Dynamic clock gating of bb_cclk is disabled. 1 indicates SATA Port0 Dynamic clock gating of bb_cclk is enabled.