Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
SATA MPHY Dynamic Power Gating Enable (PTM5) – Offset 90
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | RSVD0 (RSVD0) Reserved |
23:16 | 0h | RO | Reserved |
15:8 | 0h | RO | RSVD1 (RSVD1) Reserved |
7 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 7 (PHYDPGEP7) Same definition as bit 0, but affect port 7. Note: This bit is only applicable to project(s) that have port 7 physically. |
6 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 6 (PHYDPGEP6) Same definition as bit 0, but affect port 6. Note: This bit is only applicable to project(s) that have port 6 physically. |
5 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 5 (PHYDPGEP5) Same definition as bit 0, but affect port 5. Note: This bit is only applicable to project(s) that have port 5 physically. |
4 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 4 (PHYDPGEP4) Same definition as bit 0, but affect port 4. Note: This bit is only applicable to project(s) that have port 4 physically. |
3 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 3 (PHYDPGEP3) Same definition as bit 0, but affect port 3. Note: This bit is only applicable to project(s) that have port 3 physically. |
2 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 2 (PHYDPGEP2) Same definition as bit 0, but affect port 2. Note: This bit is only applicable to project(s) that have port 2 physically. |
1 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 1 (PHYDPGEP1) Same definition as bit 0, but affect port 1. Note: This bit is only applicable to project(s) that have port 1 physically. |
0 | 0h | RW | SATA mphy Dynamic Power Gating Enable for Port 0 (PHYDPGEP0) 0 = SATA host controller does not perform dynamic MPhy power gating. |