SLP S0 DEBUG REG0 (SLP_S0_DBG_0) – Offset 10b4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

SLP S0 DEBUG REG0 (SLP_S0_DBG_0) – Offset 10b4

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Latch SLP_S0#events (LATCH_SLPS0_EVENTS) When this bit is written to 1, the current state of SLP_S0# events is latched and captured in SLP_S0_DEBUG_REGx registers. A write of 0 has no effect though it is necessary to clear this register before writing a 1 to latch events the next time. Note that writes to this register will bring CPU out of C10 and wake PLLs in the PCH so its usage is limited to looking at certain low power entry events that are not affected by writes to this register.
30:9	0h	RO	Reserved
8	0h	RO/V	EMMC_D3_STS (EMMC_D3_STS) This bit when 1 indicates that eMMC controller is in D3 state (taking static/function disables into account as well)
7	0h	RO/V	UFS1_D3_STS (UFS1_D3_STS) This bit when 1 indicates that UFS1 controller is in D3 state (taking static/function disables into account as well)
6	0h	RO/V	UFS0_D3_STS (UFS0_D3_STS) This bit when 1 indicates that UFS0 controller is in D3 state (taking static/function disables into account as well)
5	0h	RO/V	SATA_D3_STS (SATA_D3_STS) This bit when 1 indicates that SATA controller is in D3 state (taking static/function disables into account as well)
4	0h	RO	Reserved
3	0h	RO/V	LPIO_D3_STS (LPIO_D3_STS) This bit when 1 indicates that LPIO controller is in D3 state (taking static/function disables into account as well)
2	0h	RO/V	XHCI_D3_STS (XHCI_D3_STS) This bit when 1 indicates that XHCI controller is in D3 state (taking static/function disables into account as well)
1	0h	RO/V	OTG_D3_STS (OTG_D3_STS) This bit when 1 indicates that DCI (OTG) controller is in D3 state (taking static/function disables into account as well)
0	0h	RO/V	AUDIO_D3_STS (AUDIO_D3_STS) This bit when 1 indicates that Audio DSP controller is in D3 state (taking static/function disables into account as well)