SMI Control and Enable (SMI_EN) – Offset 30 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

SMI Control and Enable (SMI_EN) – Offset 30

This register is symmetrical to the SMI Status Register.

Bit Range	Default	Access	Field Name and Description
31	0h	RW	XHCI SMI Enable (XHCI_SMI_EN) Software sets this bit to enable XHCI SMI events.
30	0h	RW	ME SMI Enable (ME_SMI_EN) Software sets this bit to enable ME SMI# events.
29	0h	RW	LPSS SMI Enable (LPSS_SMI_EN) Software sets this bit to enable I3C, I2C, UART, GSPI SMI events
28	0h	RW/L	eSPI SMI Enable (ESPI_SMI_EN) Software sets this bit to enable eSPI SMI events. NOTE: When the ESPI_SMI_LOCK bit is set, this bit cannot be changed.
27	0h	RW/1S	GPIO Unlock SMI Enable (GPIO_UNLOCK_SMI_EN) Setting this bit will cause the PCH to generate an SMI# when the GPIO_UNLOCK_SMI_STS bit is set in the SMI_STS register. Once written to '1' , this bit can only be cleared by RSMRST#.
26	0h	RO	Reserved (Rsvd26) Reserved
25	0h	RW	SDX SMI Enable (SDX_SMI_EN) Software sets this bit to enable SCC SMI events
24:19	0h	RO	Reserved (RSVD24_18) Reserved
18	0h	RW	THERM SMI Enable (THERM_SMI_EN) Software sets this bit to enable Thermal SMI# events.
17	0h	RW	Legacy USB 2 Enable (LEGACY_USB2_EN) Enables legacy USB2 logic to cause SMI#.
16:15	0h	RO	Reserved (Rsvd) Reserved
14	0h	RW	Periodic Enable (PERIODIC_EN) Setting this bit will cause the PCH to generate an SMI# when the PERIODIC_STS bit is set in the SMI_STS register.
13	0h	RW/L	TCO Enable (TCO_EN) 1 = Enables the TCO logic to generate SMI#. 0 = Disables TCO logic generating an SMI#. If the NMI2SMI_EN bit is set, then SMI's that are caused by NMI's (i.e. rerouted) will not be gated by the TCO_EN bit . Even if the TCO_EN bit is 0, the NMI's will still be routed to cause the SMI#. NOTE: This bit can not be written once the TCO_LOCK bit (at offset 08h of TCO I/O Space) is set. This prevents unauthorized software from disabling the generation of TCO-based SMI's
12	0h	RO	Reserved (Rsvd_1) Reserved
11	0h	RW	MCSMI Enable (MCSMI_EN) Software sets this bit to 1 to enables the PCH to trap access to the microcontroller range (62h or 66h). A 'trapped' cycles will be claimed by the PCH, but not forwarded to eSPI. An SMI# will also be generated.
10:8	0h	RO	Reserved (Rsvd_2) Reserved
7	0h	WO	BIOS_RLS (BIOS_RLS) Enables the generation of an SCI interrupt for ACPI software when a one is written to this bit position by BIOS software. This bit always reads a zero. NOTE: GBL_STS being set will cause an SCI, even if the SCI_EN bit is not set. Software must take great care not to set the BIOS_RLS bit (which causes GBL_STS to be set) if the SCI handler is not in place.
6	0h	RW	Software SMI Timer Enable (SWSMI_TMR_EN) Software sets this bit to a 1 to start the Software SMI# Timer. When the timer expires (depending on the SWSMI_RATE_SEL bits), it will generate an SMI# and set the SWSMI_TMR_STS bit. The SWSMI_TMR_EN bit will remain at 1 until software sets it back to 0. Clearing the SWSMI_TMR_EN bit before the timer expires will reset the timer and the SMI# will not be generated. The default for this bit is 0.
5	0h	RW	APMC Enable (APMC_EN) If set, this enables writes to the APM_CNT register to cause an SMI#
4	0h	RW	SMI On Sleep Enable (SMI_ON_SLP_EN) If this bit is set, the PCH will generate an SMI# when a write access attempts to set the SLP_EN bit (in the PM1_CNT register). Furthermore, the PCH will not put the system to a sleep state. This allows the SMI# handler work around chip-level bugs. It is expected that the SMI# handler will turn off the SMI_ON_SLP_EN bit before actually setting the SLP_EN bit.
3	0h	RW	Legacy USB Enable (LEGACY_USB_EN) Enables legacy USB circuit to cause SMI#.
2	0h	RW	BIOS Enable (BIOS_EN) Enables the generation of SMI# when ACPI software writes a 1 to the GBL_RLS bit. Note that if the BIOS_STS bit, which gets set when software writes a 1 to GBL_RLS bit, is already a 1 at the time that BIOS_EN becomes 1, an SMI# will be generated when BIOS_EN gets set.
1	1h	RW/1S/V	End of SMI (EOS) This bit controls the arbitration of the SMI signal to the processor. This bit must be set in order for the PCH to assert SMI# low to the processor after SMI# has been asserted previously. Once the ICH asserts SMI# low, the EOS bit is automatically cleared. In the SMI handler, the CPU should clear all pending SMIs (by servicing them and then clearing their respective status bits), set the EOS bit, and exit SMM. This will allow the SMI arbiter to reassert SMI upon detection of an SMI event and the setting of a SMI status bit. The SMI# signal will go inactive for 4 PCI clocks.
0	0h	RW/L	Global SMI Enable (GBL_SMI_EN) When set, this bit enables the generation of SMIs in the system upon any enabled SMI event. This bit is reset by a PCI reset event. If this bit is not set, no SMI# will be generated. NOTE: When the SMI_LOCK bit is set, this bit cannot be changed.