Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
SMI Status (GPI_SMI_STS_GPP_C_0) – Offset 284
Refer to Register Field for detail
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:24 | 0h | RO | Reserved (RSVD_0) Reserved |
23 | 0h | RW/1C/V | GPI SMI Status (GPI_SMI_STS_GPP_C_23) Same description as bit 22. |
22 | 0h | RW/1C/V | GPI SMI Status (GPI_SMI_STS_GPP_C_22) This bit is set to '1' by hardware when a level event (See RxEdCfg, RxInv) is detected, and all the following conditions are true: |
21:0 | 0h | RO | Reserved |