SPI CS Control (SPI_CS_CONTROL) – Offset 224 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

SPI CS Control (SPI_CS_CONTROL) – Offset 224

Bit Range	Default	Access	Field Name and Description
31:16	0h	NA	reserved (reserved0) Reserved
15	1h	RW	cs3_polarity (cs3_polarity) This Bit selects the Inactive/Idle polarity of SPI CS2 Signal. The steering logic will ensure that when switching to another active SPI CS port the inactive port will be forced to the inactive polarity 0 = Low 1 = High
14	1h	RW	cs2_polarity (cs2_polarity) This Bit selects the Inactive/Idle polarity of SPI CS2 Signal. The steering logic will ensure that when switching to another active SPI CS port the inactive port will be forced to the inactive polarity 0 = Low 1 = High
13	1h	RW	cs1_polarity (cs1_polarity) This Bit selects the Inactive/Idle polarity of SPI CS2 Signal. The steering logic will ensure that when switching to another active SPI CS port the inactive port will be forced to the inactive polarity 0 = Low 1 = High
12	1h	RW	cs0_polarity (cs0_polarity) This Bit selects the Inactive/Idle polarity of SPI CS2 Signal. The steering logic will ensure that when switching to another active SPI CS port the inactive port will be forced to the inactive polarity 0 = Low 1 = High
11:10	0h	NA	reserved_11_10 (reserved_11_10) Reserved
9:8	0h	RW	cs1_output_sel (cs1_output_sel) These Bits select which SPI CS Signal is to be driven by the SSP Frame (CS). The steering logic will ensure that when switching to another active SPI CS port the inactive port will be forced to the inactive polarity defined by the corresponding SPI CS Polarity Bit, 00 = CS 0, 01 = CS 1 , 10 = CS 2, 11 = CS3
7:2	0h	NA	reserved_7_2 (reserved_7_2) Reserved
1	0h	RW	cs_state (cs_state) Manual SW control of SPI Chip Select (CS) 0 = CS is set to low 1 = CS is set to high
0	0h	RW	cs_mode (cs_mode) SPI Chip Select Mode Section. 0 = HW Mode- CS is under HW control, 1 = SW Mode CS is under SW Control using cs_state bit