SS and FS Spike Suppression Limit (IC_FS_SPKLEN) – Offset a0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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SS and FS Spike Suppression Limit (IC_FS_SPKLEN) – Offset a0

This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS or FS modes.
The relevant I2C requirement is tSP as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.

Bit Range	Default	Access	Field Name and Description
31:8	0h	RO	Reserved (RSVD_IC_FS_SPKLEN)
7:0	7h	RW	IC_FS_SPKLEN (IC_FS_SPKLEN) This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled, whichcorresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 2 being set.

Bit Range

Default

Access

Field Name and Description

31:8

Reserved (RSVD_IC_FS_SPKLEN)

7:0

IC_FS_SPKLEN (IC_FS_SPKLEN)

This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that are filtered out by the spike suppression logic.
This register can be written only when the I2C interface is disabled, whichcorresponds to the IC_ENABLE register being set to 0. Writes at other times have no effect.
The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 2 being set.

HS Spike Suppression Limit (IC_HS_SPKLEN)

I2C Enable Status (IC_ENABLE_STATUS) HS Spike Suppression Limit (IC_HS_SPKLEN)