Status and Command (BIOS_SPI_STS_CMD) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Status and Command (BIOS_SPI_STS_CMD) – Offset 4

This is a standard PCI config register. See the PCI spec for bit descriptions.

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1C/V	Detected Parity Error (DPE) 0 = No parity error detected by the controller. 1 = The controller detects a parity error on its interface
30	0h	RW/1C/V	Signaled System Error (SSE) 0 = No SERR# detected by the controller. 1 = The controller detects a SERR# on its interface
29	0h	RO	Received Master Abort (RMA) Hardwired to 0.
28	0h	RO	Received Target Abort (RTA) Hardwired to 0.
27	0h	RW/1C/V	Signaled Target Abort (STA)
26:25	0h	RO	Devsel Timing (DEVT)
24	0h	RO	Master Data Parity Error (MDPE)
23	0h	RO	Fast Back to Back Capable (FBTBC) Has no meaning on the HW.
22	0h	RO	Reserved (RSVD0) Reserved (RSVD)
21	0h	RO	66 Mhz Capable (MCAP) Not 66 MHz capable device. Has no meaning on the HW
20	0h	RO	Capablities List (CAPL) Hardwired to 0 indicating that a Capabilities List is not present.
19	0h	RO	Interrupt Status (INTS) Hardwired to 0.
18:11	0h	RO	Reserved (RSVD1) Reserved.
10	1h	RO	Interrupt Disable (INTD) 0 = Interrupt is enabled 1 = Interrupt is disabled
9	0h	RO	Fast Back to Back Enable (FBTBEN) Hardwired to 0
8	0h	RW	System Error Enable (SERREN) 0 = SERR# is Disabled 1 = SERR# is Enabled
7	0h	RO	Reserved (RSVD) Reserved.
6	0h	RW	Parity Error Response (PERRR) Hardwired to 0. No response to parity errors from the controller.
5	0h	RO	Reserved
4	0h	RO	Memory Write and Invalidate Enable (MWRIEN) 0 = Disabled 1 = Enabled
3	0h	RO	Special Cycles (SPCYC) Hardwired to 0.
2	0h	RW	Bus Master Enable (BME) 0 = Disabled 1 = Enabled
1	0h	RW	Memory Space Enable (MSE) 0 = Disables memory mapped Configuration space. 1 = Enables memory mapped Configuration space.
0	0h	RO	IO Space Enable (IOSE) 0 = Disabled 1 = Enabled

Revision ID and Class Code (BIOS_SPI_CC_RID)

Device ID and Vendor ID (BIOS_SPI_DID_VID) Revision ID and Class Code (BIOS_SPI_CC_RID)