Status And Command (STATUSCOMMAND) – Offset 4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Status And Command (STATUSCOMMAND) – Offset 4

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1C	Detected Parity Error (DPE) Detected Parity Error
30	0h	RW/1C	Signaled System Error (SSE) Signaled System Error
29	0h	RW/1C	Rma Field (RMA) Received Master Abort
28	0h	RW/1C	Rta Field (RTA) Received Target Abort
27:25	0h	RO	Reserved Field (RESERVED0) This Field Is Reserved
24	0h	RW/1C	Master Data Parity Error (MDPE) Master Data Parity Error
23:21	0h	RO	Reserved Field (RESERVED1) This Field Is Reserved
20	1h	RO	Cap List Field (CAPLIST) Capabilities List: Indicates that the controller contains a capabilities pointer list
19	0h	RO	Intrerrupt Status Field (INTR_STATUS) Interrupt Status: This bit reflects state of interrupt in the device
18:16	0h	RO	Reserved Field (RESERVED2) This Field Is Reserved
15:11	0h	RO	Reserved Field (RESERVED3) This Field Is Reserved
10	0h	RW	Interrupt Disable Field (INTR_DISABLE) If '1', SB Interrupt generation is disabled If '0', SB Interrupt generation is enabled
9	0h	RO	Reserved Field (RESERVED4) This Field Is Reserved
8	0h	RW	Serr Enable Field (SERR_ENABLE) SERR Enable Not implemented
7	0h	RO	Reserved Field (RESERVED5) This Field Is Reserved
6	0h	RW	Parity Error Response Enable (PERE) Parity Error Response Enable
5:3	0h	RO	Reserved Field (RESERVED6) This Field Is Reserved
2	0h	RW	Bme Field (BME) Bus Master Enable
1	0h	RW	Mse Field (MSE) Memory Space Enable
0	0h	RO	Reserved Field (RESERVED7) This Field Is Reserved

Revision Id And Class Code (REVCLASSCODE)

Device Id And Vendor Id Register (DEVVENDID) Revision Id And Class Code (REVCLASSCODE)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Status And Command (STATUSCOMMAND) – Offset 4