Status (SSSR) – Offset 8 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Status (SSSR) – Offset 8

The Enhanced SSP Status registers contain bits that signal overrun errors as well as the Transmit and Receive FIFO service requests. Each of these hardware-detected events signals an Interrupt request to the Interrupt controller. The Status register also contains flags that indicate when the Enhanced SSP is actively transmitting data, when the Transmit FIFO is not full, and when the Receive FIFO is not empty. One Interrupt signal is sent to the Interrupt Controller for each SSP. These events can cause an Interrupt: End-of-Chain, Receiver Time-out, Peripheral Trailing Byte, Receive FIFO overrun, Receive FIFO request, and Transmit FIFO request

Bit Range	Default	Access	Field Name and Description
31:22	0h	NA	RSVD2 (RSVD2) Reserved
21	0h	RW/1C	Transmit FIFO Under Run (TUR) Transmit FIFO Under Run The SSSR.TUR bit is a read-write, one-to-clear status bit that indicates that the transmitter tried to send data from the Transmit FIFO when the Transmit FIFO was empty. When the SSSR.TUR bit is set, an interrupt is generated to the CPU that can be locally masked by the SSCR0.TIM bit. The setting of the SSSR.TUR bit does not, however, generate any DMA service request. The SSSR.TUR bit remains set until cleared by software writing a 1 to this bit which will also reset its Interrupt request; writing a 0 to this bit does not affect SSSR.TUR status. This bit can only be set when the Enhanced SSP is a target to the FRAME signal (SSCR1.SFRMDIR = 1), or if the Enhanced SSP is a master to the FRAME signal and the Enhanced SSP is in Network mode, and will not be set if the Enhanced SSP is in Receive-Without- Transmit mode (SSCR1.RWOT =1). 0 = Transmit FIFO has not experienced an under run 1 = Attempted read from the transmit FIFO when the FIFO was empty, request interrupt.
20	0h	NA	Reseved (Reseved) Reseved
19	0h	RW/1C	Receiver Time-out Interrupt (TINT) Receiver Time-out Interrupt The SSSR.TINT bit is a read-write bit that is set to 1 when the Receive FIFO has been idle (no samples received) for a period of time defined by the value programmed within the Time-Out register (SSTO). This interrupt can be masked by the SSCR1.TINTE bit. The SSSR.TINT bit is cleared by programmers by writing a 1 to it. 0 = No receiver time-out pending 1 = Receive FIFO has been idle for period defined by SSTO
18	0h	RW/1C	Peripheral Trailing Byte Interrupt (PINT) Peripheral Trailing Byte Interrupt This feature is not recommended for use in the LPSS implementation. 0 = No peripheral trailing byte interrupt pending 1 = Peripheral trailing byte interrupt pending.
17:8	f0h	NA	RSVD (RSVD) Reserved
7	0h	RW/1C	Receive FIFO Overrun (ROR) Receive FIFO Overrun The receiver overrun status bit SSSR.ROR is a read-write bit that is set when the Receive logic attempts to place data into the Receive FIFO after it has been completely filled. If the Receive FIFO is full and new data is received, the SSSR.ROR bit is set, and the newly received data is discarded. This process is repeated for each new data - chunk received until at least one empty FIFO entry exists. When the SSSR.ROR bit is set, an Interrupt is generated to the CPU that can be locally masked by the SSCR0.RIM bit. The setting of the SSSR.ROR bit does not, however, generate any DMA service request. The SSSR.ROR bit remains set until cleared by software writing a 1 to this bit which will also reset its Interrupt request; writing a 0 to this bit does not affect SSSR.ROR status. 0 = Receive FIFO has not experienced an overrun 1 = Attempted data write to full receive FIFO, request interrupt
6	0h	RO	Receive FIFO Service Request (RFS) Receive FIFO Service Request The receive FIFO service request flag SSSR.RFS is a read-only bit that is set to generate an Interrupt when the Receive FIFO requires service to prevent an overrun. SSSR.RFS is set any time the Receive FIFO has more entries of valid data than the number indicated by the Receive FIFO Trigger threshold, and it is cleared when it has the same or fewer entries than the threshold value. When the SSSR.RFS bit is set, an Interrupt is generated unless the receive FIFO interrupt request enable (SSCR1.RIE) bit is cleared. Also, the setting of the SSSR.RFS bit will signal a DMA service request if the SSCR1.RSRE bit is set. After the CPU or DMA reads the FIFO such that it has the same or fewer entries than the SIRF.WMRF value, the SSSR.RFS flag (and the service request and/or Interrupt) is automatically cleared. Software should not set both the SSCR1.RSRE and the SSCR1.RIE bits. 0 = Receive FIFO level is at or below the water mark for the SPI receive FIFO (WMRF) or SSP disabled 1 = Receive FIFO level exceeds the water mark for the SPI receive FIFO (WMRF) , request interrupt
5	0h	RO	Transmit FIFO Service Request (TFS) Transmit FIFO Service Request The transmit FIFO service request flag SSSR.TFS is a read-only bit that is set to generate an Interrupt when the Transmit FIFO requires service to prevent an underrun. SSSR.TFS is set any time the Transmit FIFO has the same or fewer entries of valid data than indicated by the Transmit FIFO Trigger threshold, and it is cleared when it has more entries of valid data than the threshold value (the service request is triggered when the number of FIFO entries is less than or equal to 1 + LWMTF). When the SSSR.TFS bit is set, an Interrupt is generated unless the transmit FIFO interrupt request enable (SSCR1.TIE) bit is cleared. Also, the setting of the SSSR.TFS bit will generate a DMA service request if the SSCR.TSRE bit was set. After the CPU or the DMA fills the FIFO such that it exceeds the threshold, the SSSR.TFS flag (and the service request and/or Interrupt) is automatically cleared. If the threshold has not been exceeded, another request will be made. Software should not set both the SSCR1.TSRE and the SSCR1.TIE bits. 0 = Transmit FIFO level exceeds the Low Water Mark Transmit FIFO (SITF.LWMTF), or SSP disabled 1 = Transmit FIFO level is at or below the Low Water Mark Transmit FIFO (SITF.LWMTF), request interrupt
4	0h	RO	Busy (BSY) The Enhanced SSP busy SSSR.BSY flag is a read-only bit that is set when the SSP is actively transmitting and/or receiving data, and is cleared when the SSP is idle or disabled (SSCR0.SSE=0). This bit does not generate an Interrupt. 0 = SSP is idle or disabled 1 = SSP currently transmitting or receiving a frame
3	0h	RO	Receive FIFO Not Empty (RNE) Receive FIFO Not Empty The receive FIFO not empty flag SSSR.RNE is a read-only bit that is set whenever the Receive FIFO contains one or more entries of valid data, and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remaining bytes of data from the Receive FIFO since CPU Interrupt requests are made only when the Receive FIFO Trigger threshold has been met or exceeded. This bit does not generate an Interrupt. 0 = Receive FIFO is empty 1 = Receive FIFO is not empty
2	1h	RO	Transmit FIFO Not Full (TNF) Transmit FIFO Not Full The receive FIFO not empty flag SSSR.RNE is a read-only bit that is set whenever the Receive FIFO contains one or more entries of valid data, and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remaining bytes of data from the Receive FIFO since CPU Interrupt requests are made only when the Receive FIFO Trigger threshold has been met or exceeded. This bit does not generate an Interrupt. 0 = Transmit FIFO is full 1 = Transmit FIFO is not full
1:0	0h	NA	RSVD8 (RSVD8) Reserved