Stream Synchronization (SSYNC) – Offset 38 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Stream Synchronization (SSYNC) – Offset 38

To synchronize two or more streams, the corresponding SSYNC bits for the streams to be synchronized should be set to 1, before the RUN bit for each stream is set. The RUN bit for the corresponding stream must be set to 1 (and FIFORDY=1) prior to that streams SSYNC bit being written to 0. To start multiple streams synchronously, the stream sync bits for those streams should be written to 0 at the same time. For all SSYNC bits on output engines that transition from 1 to 0 on the same write, the formatter will deliver a sample over the link in the same 48kHz frame. For all SSYNC bits on input engines that transition from 1 to 0 on the same write, the formatter will take stream data off the link and place it in the FIFO.If synchronization is not desired, the stream synchronization bits may be left 0, and the stream will simply begin running normally when the streams RUN bit is set.

Bit Range	Default	Access	Field Name and Description
31:19	0h	RO	Reserved (RSVD6) This is a Reserved Register
18:0	0h	RW/L	Stream Synchronization Bits (SSYNC) The Stream Synchronization bits, when set to 1, block data from being sent on or received from the link. Each bit controls the associated Stream Descriptor- bit 0 corresponds to the first Stream Descriptor, etc.To synchronously start a set of DMA engines, the bits in the SSYNC register are first set to a 1. The RUN bits for the associated Stream Descriptors are then set to a 1 to start the DMA engines. When all streams are ready (FIFORDY=1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame.To synchronously stop streams, first the bits are set in the SSYNC register, and then the individual RUN bits in the Stream Descriptors are cleared by software.The streams are numbered and the SSYNC bits assigned sequentially, based on their order in the register set. With the introduction of multiple link segments for the HD Audio controller and the potential of running each link on independent and asynchronous clocks, it should be noted that SSYNC can only be used to synchronously start or stop two or more streams only if these streams are mapped to a common link segment.

Bit Range

Default

Access

Field Name and Description

31:19

Reserved (RSVD6)

This is a Reserved Register

18:0

RW/L

Stream Synchronization Bits (SSYNC)

The Stream Synchronization bits, when set to 1, block data from being sent on or received from the link. Each bit controls the associated Stream Descriptor- bit 0 corresponds to the first Stream Descriptor, etc.To synchronously start a set of DMA engines, the bits in the SSYNC register are first set to a 1. The RUN bits for the associated Stream Descriptors are then set to a 1 to start the DMA engines. When all streams are ready (FIFORDY=1), the associated SSYNC bits can all be set to 0 at the same time, and transmission or reception of bits to or from the link will begin together at the start of the next full link frame.To synchronously stop streams, first the bits are set in the SSYNC register, and then the individual RUN bits in the Stream Descriptors are cleared by software.The streams are numbered and the SSYNC bits assigned sequentially, based on their order in the register set. With the introduction of multiple link segments for the HD Audio controller and the potential of running each link on independent and asynchronous clocks, it should be noted that SSYNC can only be used to synchronously start or stop two or more streams only if these streams are mapped to a common link segment.