SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) – Offset 80ec - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

SuperSpeed Port Link Control (HOST_CTRL_PORT_LINK_REG) – Offset 80ec

SuperSpeed Port Link Control

Bit Range	Default	Access	Field Name and Description
31:27	3h	RW	Force LTSSM State (FORCE_LTSSM_ST) LTSSM state to be forced This value is for test purpose only.
26	0h	RW	Direct Link LTSSM State (DL_LTSSM_ST) 0: Normal operation mode 1: Direct link to a specific state specified by bit 31:27 This bit is for test purpose only. It shall be written 0 in normal operation mode.
25	0h	RW	Direct Link To U0 (DL_U0) 0: Normal operation mode 1: Direct link to U0 This bit is for test purpose only. It shall be written 0 in normal operation mode.
24:21	0h	RW	Forced Compliance Pattern (FORCED_CMP_PAT) Compliance pattern to be forced to enter compliance mode This value is for test purpose only.
20	0h	RW	Enable Link Error Count (EN_LES_CNT) 0: Disable port link error count 1: Enable port link error count
19	0h	RW	TS rcv to complete U1/U2/U3 exit LFPS handshake (TS_RCV_UX_EXIT_LFPS_HS) 1: enable TS receive to complete U1/U2/U3 exit LFPS handshake 0: disable TS receive to complete U1/U2/U3 exit LFPS handshake
18	0h	RW	Enable IDLE Receive to exit Polling.Config and Recov.Config (EN_LOGIC_TO_EXIT_POLLCONF_AND_RECCONF) 1: enable logic idle receive to exit Polling.Configuration and Recovery.Configuration 0: disable logic idle receive to exit Polling.Configuration and Recovery.Configuration
17	0h	RW	Port Initialization Timeout Value (PORT_INTIL_TIMEOUT_VAL) This bit specifies the port initialization timeout value. 0: 20us - 21us 1: 19us - 20us
16:15	0h	RW	PHY Low Power Latency (PHY_LP_LAT) This field defines the latency to drive the PHY to enter low power mode 0: 4 cycles 1: 8 cycles 2: 16 cycles 3: 32 cycles
14:12	0h	RW	Link Recovery Minimum Time (LR_MIN_TM) This value defines the minimum time for the link to stay in Recovery.Active other than from U3. The granuity is 128us.
11:9	0h	RW	Link Polling Minimum Time (LP_MIN_TM) This value defines the minimum time for the link to stay in Polling.Active and Recovery.Active from U3. The granuity is 128us.
8	0h	RW	Force Link Accept PM Command (FORCE_LA_PMC) 0: Normal operation mode 1: Force link to accept power management command
7	0h	RW	Direct Link Recovery U0 (DL_REC_U0) 0: Normal operation mode 1: Direct link to Recovery from U0
6	0h	RW	Link Fast Training Mode (LINK_FTM) 0: Normal operation mode 1: Link fast training mode This bit should be written 0 in normal operation.
5	0h	RW	Disable Link Scrambler (DIS_LINK_SCRAM) 0: Enable link scrambler 1: Disable link scramber
4	0h	RW	Direct Link U3 From U0 (DL_U3_U0) 0: Normal operation mode 1: Direct link to U3 from U0 This bit is for test purpose only. It shall be written 0 in normal operation mode.
3	0h	RW	Direct Link U3 From U0 (DL_U2_U0) 0: Normal operation mode 1: Direct link to U2 from U0 This bit is for test purpose only. It shall be written 0 in normal operation mode.
2	0h	RW	Direct Link U3 From U0 (DL_U1_U0) 0: Normal operation mode 1: Direct link to U1 from U0 This bit is for test purpose only. It shall be written 0 in normal operation mode.
1	0h	RW	Enable Link Loopback Master Mode (EN_LINK_LB_MAST) 0: Disable link loopback master mode 1: Enable link loopback master mode
0	0h	RW	Disable Link Compliance Mode (DIS_LINK_CM) 0: Enable link compliance mode 1: Disable link compliance mode