SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR) – Offset 98 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
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SMBus MMIO and I/O
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SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR) – Offset 98

Bit Range	Default	Access	Field Name and Description
31:4	0h	RO	SW LTR Update MMIO Offset Location (SWLTRLOC) This register contains the location pointer to the SW LTR register in MMIO space, as an offset from the specified BAR. The value of this register is a dont care, if the Valid bit is not set
3:1	0h	RO	Base Address Register Number (BARNUM) Contains the 0s based AR Number of the BAR which contains the location of the SW LTR MMIO register. When counting BAR Numbers, all BARs, regardless of size and type, consume one BAR Number. Bar 0 is the 1st BAR. The value of this register is a dont care, if the Valid bit is not set.
0	0h	RO	AW LTR Valid (VALID) Set to 1 to indicate that the function has implemented a SW LTR register as specified in the DevIdle that can be located using the SWLTRLOC register and BARNUM. Set to 0 to indicate that the function has not implemented a SW LTR register that is compliant to the DevIdle definition. This could be because the function has not implemented SW LTR at all, or has a device specific version of SW LTR.

Bit Range

Default

Access

Field Name and Description

31:4

SW LTR Update MMIO Offset Location (SWLTRLOC)

This register contains the location pointer to the SW LTR register in MMIO space, as an offset from the specified BAR.
The value of this register is a dont care, if the Valid bit is not set

3:1

Base Address Register Number (BARNUM)

Contains the 0s based AR Number of the BAR which contains the location of the SW LTR MMIO register.
When counting BAR Numbers, all BARs, regardless of size and type, consume one BAR Number. Bar 0 is the 1st BAR.
The value of this register is a dont care, if the Valid bit is not set.

AW LTR Valid (VALID)

Set to 1 to indicate that the function has implemented a SW LTR register as specified in the DevIdle that can be located using the SWLTRLOC register and BARNUM.
Set to 0 to indicate that the function has not implemented a SW LTR register that is compliant to the DevIdle definition. This could be because the function has not implemented SW LTR at all, or has a device specific version of SW LTR.

Device Idle Pointer Register (THC_CFG_DEVIDLEPTR)

Vendor Specific Header (THC_CFG_VSHDR) Device Idle Pointer Register (THC_CFG_DEVIDLEPTR)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

SW LTR Pointer Regsiter (THC_CFG_SWLTRPTR) – Offset 98