TCO Configuration (TCOCFG) – Offset 0 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
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GPIO Commumity 3
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GPIO Commumity 5
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Integrated Sensor Hub (ISH) PCI Configuration
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- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
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SATA Port 4 ABAR
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SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
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SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
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- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

TCO Configuration (TCOCFG) – Offset 0

Bit Range	Default	Access	Field Name and Description
31:8	0h	RSV	Reserved (RSVD) Reserved
7	0h	RW	TCO IRQ Enable (IE) When set, TCO IRQ is enabled, as selected by the TCO_IRQ_SEL field. When cleared, TCO IRQ is disabled.
6:3	0h	RSV	Reserved (RSVD_1) Reserved
2:0	0h	RW	TCO IRQ Select (IRQSEL) Specifies on which IRQ the TCO will internally appear. If not using the APIC, the TCO interrupt must be routed to IRQ9-11, and that interrupt is not sharable with the SERIRQ stream, but is shareable with other PCI interrupts. If using the APIC, the TCO interrupt can also be mapped to IRQ20-23, and can be shared with other interrupt. Bits TCO Map 000 IRQ9 (maps to 8259 and APIC) 001 IRQ10 (maps to 8259 and APIC) 010 IRQ11 (maps to 8259 and APIC) 011 Reserved 100 IRQ20 (maps to APIC) 101 IRQ21 (maps to APIC) 110 IRQ22 (maps to APIC) 111 IRQ23 (maps to APIC) When setting the these bits, the IE bit should be cleared to prevent glitching. When the interrupt is mapped to APIC interrupts 9, 10 or 11, the APIC should be programmed for active-high reception. When the interrupt is mapped to APIC interrupts 20 through 23, the APIC should be programmed for active-low reception.

General Control (GC)

SMBus PCR General Control (GC)