THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_1) – Offset 1170 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

THC Device Address for the bulk/touch data read for the 2nd RXDMA (THC_M_PRT_RD_BULK_ADDR_1) – Offset 1170

Bit Range	Default	Access	Field Name and Description
31:0	1000h	RW/O	THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR) THC Device Address for the bulk/touch data read. In SPI mode, the touch data read cycles addresses start from the bulk address specified in this register and increment every packet until the end of the microframe. The touch read address resumes using the address in this register at the beginning of every new microframe. SW is responsible to program this register correctly, and make sure all resulting touch cycles will not exceed the touch device's bulk address space or roll over. Otherwise, THC's behavior is undefined. Note: For SPI devices, only 24bit addressing space is supported. Default to 0x1000.

Bit Range

Default

Access

Field Name and Description

31:0

1000h

RW/O

THC Device Address for the bulk/touch data read for the 1st RXDMA (THC_M_PRT_RD_BULK_ADDR)

THC Device Address for the bulk/touch data read.
In SPI mode, the touch data read cycles addresses start from the bulk address specified in this register and increment every packet until the end of the microframe. The touch read address resumes using the address in this register at the beginning of every new microframe.
SW is responsible to program this register correctly, and make sure all resulting touch cycles will not exceed the touch device's bulk address space or roll over. Otherwise, THC's behavior is undefined. Note: For SPI devices, only 24bit addressing space is supported.

Default to 0x1000.

THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1)

Touch Sequencer GuC Tail Offset Initial Value for the 1st RXDMA (THC_M_PRT_GUC_OFFSET_INITVAL_1) THC Gfx/SW Doorbell Count from the 1st Stream RXDMA on this port (THC_M_PRT_DB_CNT_1)