THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2) – Offset 120c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

THC Read DMA Control for the 2nd RXDMA (THC_M_PRT_READ_DMA_CNTRL_2) – Offset 120c

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1S/V	THC PRD CB Pointer Reset for the 2nd RXDMA (TPCPR) Setting this bit to a 1b resets DMA circular buffers read and write pointers to 00h. After the DMA CB pointers have been reset to 00h, hardware clears this bit to 0. SW can only reset tail offset when active and start are 0, i.e. DMA is idle.
30	1h	RO	Update HwStatus for the 2nd RXDMA (UHS) If set, the HwStatus field of each PRD entry (for each PRD table) bit is updated (successful or error).
29	0h	RW	Stop on Overflow for the 2nd RXDMA (SOO) When set, HW will clear the Start bit, upon detection of a DMA Buffer overflow, and stop read DMA operations. An overflow condition occurs when the read and write pointers contain the same value. It will stop both DMA engine.
28	0h	RW/L	Interrupt SW Enable on DMA Device Interrupt for the 2nd RXDMA (INT_SW_DMA_EN) When set to 1, an interrupt is generated to host SW even when a "touch data ready" interrupt cause is read from the touch IC INT_CAUSE register. The read DMA in the HW sequencer is not running to read the touch data in this case. The non-DMA device inband interrupt status bit is set. SW is expected to read the device interrupt cause register and if it sees the 01 (touch data ready) is set, it could potentially read the touch device using PIO.
27:24	0h	RO	Reserved (RSVD_27_24) Reserved.
23:16	0h	RW/V	THC PRD CB Write Pointer for the 2nd RXDMA (TPCWP) The write pointer is updated by SW. The write pointer points to location in the DMA CB, where the next PRD table is going to be stored. SW needs to ensure that this pointer rolls over once the circular buffer's depth has been traversed with Bit[7] as the rollover bit. E.g. if the DMA CB depth is equal to 5 entries (0100b), then the write pointers will follow this pattern (SW is required to honor this behavior) 00h 01h 02h 03h 04h 80h 81h 82h 83h 84h 00h 01h ..
15:8	0h	RO/V	THC PRD CB Read Pointer for the 2nd RXDMA (TPCRP) DMA HW consumes the PRD tables in the CB, one PRD entry at a time until the EOP bit is found set in a PRD entry. At this point HW increments the PRD read pointer. Thus, the read pointer points to the PRD which the DMA engine is currently processing. This pointer rolls over once the circular buffer's depth has been traversed with bit[7] the Rollover bit. E.g. if the DMA CB depth is equal to 4 entries (0011b), then the read pointers will follow this pattern (HW is required to honor this behavior) 00h 01h 02h 03h 80h 81h 82h 83h 00h 01h ...
7	0h	RW	Interrupt Enable on DMA Completion for the 2nd RXDMA (IE_DMACPL) When set, interrupt is generated upon completion of DMA (DMACPL_STS=1).
6	0h	RO	Reserved (RSVD_6) Reserved.
5	0h	RW	Interrupt Enable at EOF for the 2nd RXDMA (IE_EOF) When set, an interrupt will be generated when EOF is detected. For raw data mode, this occurs when all micro frames have been DMA'd. For HID mode, this occurs after each HID report is DMA'd. When EGP is set, the interrupt occurs after GuC processing is complete.
4	0h	RO	Reserved (RSVD_4) Reserved.
3	0h	RW	Interrupt Enable on Stall for the 2nd RXDMA (IE_STALL) When set, an interrupt is generated to host SW when the CB read and write pointers are the same. This condition could be used to detect a stall of the GPU and subsequent buffer overrun internal to the Touch IC.
2	0h	RW	Interrupt Enable on Completion for the 2nd RXDMA (IE_IOC) When set, interrupt is generated upon completion of the PRD block transfer, with IOC=1, or when an error is encountered with the Error=1.
1	0h	RW	Interrupt Enable on Error for the 2nd RXDMA (IE_ERROR) When set, interrupt is generated upon an read DMA error is encountered.
0	0h	RW/V	Start for the 2nd RXDMA (START) SW sets the Start bit to arm the DMA engine. Once SW sets the Start bit it cannot modify entries in the PRD table. This gives HW the option of caching the PRD table for performance reasons. SW clears the bit after the DMA completion as indicated by interrupt and/or Status bits. SW can also clear the Start bit to abort an on-going DMA operation. DMA hardware completes all the outstanding requests to system memory and then stops the PRD actions at a safe point, e.g. at a microframe boundary so that it can resumed gracefully after SW set the start bit again. HW will clear this bit upon error conditions.