Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2
ID | Date | Version | Classification |
---|---|---|---|
834576 | 10/10/2024 | 001 | Public |
THC Read Interrupt Status for the 2nd RXDMA (THC_M_PRT_READ_DMA_INT_STS_2) – Offset 1210
Bit Range | Default | Access | Field Name and Description |
---|---|---|---|
31:9 | 0h | RO | Reserved |
8 | 0h | RO/V | Active status bit for the 2nd RXDMA (ACTIVE) DMA is active and not completed. Set by HW when the Start bit is set by SW and auto-cleared by HW in the following conditions: |
7:6 | 0h | RO | Reserved (RSVD_7_6) Reserved. |
5 | 0h | RW/1C/V | Interrupt Status of EOF for the 2nd RXDMA (EOF_INT_STS) Interrupt status when an EOF is encountered. If the IE_EOF bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |
4 | 0h | RO | Reserved (RSVD_4) Reserved. |
3 | 0h | RW/1C/V | Interrupt Status of PRD table stalls bit for the 2nd RXDMA (STALL_STS) Interrupt status when the CB read and write pointers are the same. This condition could be used to detect a stall of the GPU and subsequent buffer overrun internal to the Touch IC. If the IE_STALL bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |
2 | 0h | RW/1C/V | Interrupt Status of PRD completion with IOC Equals 1 for the 2nd RXDMA (IOC_STS) An PRD entry with IOC bit set has been completed during DMA operation. If the IE_IOC bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |
1 | 0h | RW/1C/V | Error status bit for the 2nd RXDMA (ERROR_STS) Error encountered during DMA operation. An interrupt is generated if the interrupt is enabled. SW clears the bit by writing 1 to the bit. |
0 | 0h | RW/1C/V | DMA Complete bit for the 2nd RXDMA (DMACPL_STS) This bit is set upon successful completion of the DMA operation. If the IE bit is also 1, then an interrupt is generated. SW clears the bit by writing 1 to the bit. |