THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) – Offset 1040 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
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THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
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USB MMIO
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xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) – Offset 1040

Bit Range	Default	Access	Field Name and Description
31:16	0h	RW/L	THC SW Sequencing Bus Byte Count (THC_SS_BC) This field specifies the SPI read/write byte count to send out during the SW sequencing cycle. For SPI, this is a 1-based byte count for read or write. i.e. value 1 is for 1 byte and 2 is for 2 bytes. Valid values are in the range of 1-64. Any other value will result in THC_SS_ERR being set.
15:8	0h	RW/L	THC SW Sequencing Bus Command (THC_SS_CMD) In SPI port, the register read and touch data read commands are mapped to SPI read cycles. The register write and bulk write commands are mapped to SPI write cycles. The other commands are not used in SPI mode.
7:2	0h	RO	Reserved (RSVD_7_2) Reserved.
1	0h	RW/L	THC SW Sequencing Cycle Done Interrupt Enable (THC_SS_CD_IE) When set to 1, the THC asserts an interrupt request whenever the Touch Cycle Done bit is 1.
0	0h	RW/1S/V/L	THC SW Sequence Cycle Go (TSSGO) A write to this register with THC Arbiter to start a cycle. This register is cleared by hardware when the cycle is granted by the THC arbiter to run the cycle on the THC bus. When the cycle is complete, the TSSDONE bit is set. Software is forbidden to write to any register in the THC_SS_SEQ_CNTRL/DATA register between the TSSGO bit getting set and the TSSDONE bit being cleared. Any attempt to violate this rule will be ignored by hardware. Hardware allows other bits in this register to be programmed for the same transaction when writing this bit to 1. This saves an additional memory write. This bit remains set until the transaction is granted by the THC Controller's internal arbiter.

THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS)

THC Error Cause Register (THC_M_PRT_ERR_CAUSE) THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS)