THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) – Offset 1044 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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CNVi WiFi* PCI Configuration
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GPIO Commumity 0
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GPIO Commumity 2
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RTC Index
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SATA ABAR
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- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
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- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
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SATA Port 0 ABAR
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SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) – Offset 1044

Bit Range	Default	Access	Field Name and Description
31:4	0h	RO	Reserved (RSVD_31_4) Reserved.
3	0h	RO/V	THC SW Sequencing Cycle In Progress (THC_SS_CIP) Hardware sets this bit when software sets the THC Cycle Go (TSSGO) bit. This bit remains set until the cycle completes on the bus interface. Hardware automatically sets and clears this bit so that software can determine when read data is valid and/or when it is safe to begin programming the next command. Software must only program the next command when this bit is 0.
2	0h	RO	Reserved (RSVD_2) Reserved.
1	0h	RW/1C/V	THC SW Sequencing Error (THC_SS_ERR) Hardware sets this bit to 1 when any of the programmed cycle registers is written while a programmed access is already in progress. This bit remains asserted until cleared by software writing a 1 or until a partition reset occurs. Software must clear this bit before setting the THC Cycle GO bit in this register.
0	0h	RW/1C/V	THC SW Sequence Cycle Done (TSSDONE) The THC sets this bit to 1 when the SW Touch Cycle completes after software previously set the TSSGO bit. This bit remains asserted until cleared by software writing a 1 or host partition reset. When this bit is set and the THC_SS_CD_IE MSI Enable bit is set the THC controller sends MSI. Software must make sure this bit is cleared prior to enabling the TDONE MSI assertion for a new programmed access.

THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR)

THC SW sequencing Control (THC_M_PRT_SW_SEQ_CNTRL) THC SW Sequencing Data DW0 or SPI Address Register (THC_M_PRT_SW_SEQ_DATA0_ADDR)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

THC SW sequencing Status (THC_M_PRT_SW_SEQ_STS) – Offset 1044