THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) – Offset 1098 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) – Offset 1098

Bit Range	Default	Access	Field Name and Description
31:24	0h	RW	PRD Table Entry Count for WRDMA (THC_WRDMA_PTEC) The number of PRD entries in the write PRD tables. 00h: 1 PRD entry for the write PRD Table 01h: 2 PRD entries for the write PRD Table :: FFh: 256 PRD entries for each PRD Table
23	1h	RO	Update HW Status for WRDMA (THC_WRDMA_UHS) If set, the HwStatus field of each PRD entry (for each PRD table) bit is updated (successful or error).
22:4	0h	RO	Reserved (RSVD_22_4) Reserved.
3	0h	RW	Interrupt Enable on WRDMA Completion (THC_WRDMA_IE_IOC_DMACPL) When set, interrupt is generated upon completion of the Write DMA PRD table.
2	0h	RW	Interrupt Enable on IOC for WRDMA (THC_WRDMA_IE_IOC) When set, interrupt is generated upon completion of the PRD block transfer, with IOC=1, or when an error is encountered with the Error=1 in the THC_WRITE_DMA_INT_STS register.
1	0h	RW	Interrupt Enable on Error for WRDMA (THC_WRDMA_IE_IOC_ERROR) When set, interrupt is generated when an error is encountered with the Write DMA Error=1.
0	0h	RW/V	Start WRDMA (THC_WRDMA_START) SW sets the Start bit to arm the Write DMA engine. HW clears the bit after the DMA completion as indicated by interrupt and/or Status bits. SW can also clear the Start bit to abort an on-going DMA operation. In this case, HW completes all the outstanding requests to system memory and then stops the PRD actions at a safe point. SW shall poll this bit after it writes 0 to the start bit until HW completes the stop and clears the bit.

THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS)

THC Write PRD Base Address Register High (THC_M_PRT_WPRD_BA_HI) THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS)

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Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) – Offset 1098