THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS) – Offset 109c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

THC Write Interrupt Status (THC_M_PRT_WRITE_INT_STS) – Offset 109c

Bit Range	Default	Access	Field Name and Description
31:4	0h	RO	Reserved (RSVD_31_4) Reserved.
3	0h	RO/V	Active status for Write DMA (THC_WRDMA_ACTIVE) Write DMA is active. Set by HW when the Write DMA Start bit is set by SW and auto-cleared by HW in the following conditions: - The entire Write DMA operation has been completed successfully or - The Write DMA operation has been halted by software clearing the Write DMA Start bit (and no read completion pending).
2	0h	RW/1C/V	Interrupt Status for IOC for Write DMA (THC_WRDMA_IOC_STS) A PRD entry with IOC bit set has been completed during WRDMA operation. If the THC_WRDMA_IE_IOC bit is also 1, then an interrupt is generated. In polling mode, when THC_WRDMA_IE_IOC Equals to 0, SW clears the bit by writing 1 to the bit.
1	0h	RW/1C/V	Write DMA Error Status (THC_WRDMA_ERROR_STS) Error encountered during write DMA operation. If the THC_WRDMA_IE_ERROR bit is also 1, then an interrupt is generated. In polling mode, when THC_WRDMA_IE_ERROR Equals 0, SW clears the bit by writing 1 to the bit. Note: For SPI bus, there is no known error condition for this bit.
0	0h	RW/1C/V	Write DMA Completion Status bit (THC_WRDMA_CMPL_STATUS) This bit is set upon successful completion of the Write DMA operation or by the rising edge of the Error bit. If the THC_WRDMA_IE_IOC_DMACPL bit is also 1, then an interrupt is generated. In polling mode, when THC_WRDMA_IE_IOC_DMACPL=0, SW clears the bit by writing 1 to the bit.

THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR)

THC Write DMA Control (THC_M_PRT_WRITE_DMA_CNTRL) THC device address for the bulk write (THC_M_PRT_WR_BULK_ADDR)