Throttle Level (TL) – Offset 1520 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Throttle Level (TL) – Offset 1520

Bit Range	Default	Access	Field Name and Description
31	0h	RW/L	TLLOCK (TLLOCK) When set to 1, this entire register (TL) is locked and remains locked until the next platform reset
30	0h	RW/L	TT State 13 Enable (TT13EN) When set to 1 and the programmed GPIO pin (see Chapter 16) is a 1, then PMSync state 13 (now called GPIO_A) will force at least T2 state
29	0h	RW/L	TT Enable (TTEN) This is the enable bit associated with the FW control of the throttle state. This bit needs to be set in order for the FW to be able to update the throttle state based on the comparison of the T2L/T1L/T0L with the temperature. At reset, BIOS must set bits 28:0 and then do a separate write to set bit 29 to enable throttling. SW may set bit 31 at the same time it sets bit 29 if it wishes to lock the register. If SW wishes to change the values of 28:0, it must first clear the TTEN bit, then change the values in 28:0; and then re-enable TTEN. It is legal to set bits 31, 30 and 29 with the same write This bit must not be set by SW until SW has already enabled atleast one of the thermal sensor(setting TSENx.ETS bits to 1) If TTEN is written to 0, after having been enabled, then the PCH may stay in the throttling state it was in at the moment TTEN is disabled. There is no intent that the sensor be enabled for a while and then disabled and left off. It may be disabled temporarily while changing the register values, but it should not be left in the disabled state
28:20	ffh	RW/L	T2 Level (T2L) Determines the temp level for T2 state. If TTEN = 1 AND TSEN = 1 AND T2L >= TEMP.MAXTEMP[8:0] > T1L, then the system is in T2 state. If TTEN = 1 AND TSE = 1 AND TEMP.MAXTEMP [8:0] > T2L, then the system is in T3 state.SW Note: When TTEN =1 condition to satisfy is T2L > T1L > T0L NOTE: the T3 condition overrides PMSync[13] and forces the system to T3 if both cases are true
19	0h	RO	Reserved
18:10	ffh	RW/L	T1 Level (T1L) Determines the temp level for T1 state. If TTEN = 1 AND (\|TSEN) = 1 AND T1L >= TEMP.MAXTEMP[8:0] > T0L, then the system is in T1 state. SW Note: When TTEN =1 condition to satisfy is T2L > T1L > T0L
9	0h	RO	Reserved
8:0	ffh	RW/L	T0 Level (T0L) Determines the temp level for T0 state. If TEMP.MAXTEMP[8:0] <= T0L or TTEN = 0 OR (\|TSEN) = 0, then the system is in T0 state SW Note: When TTEN =1 condition to satisfy is T2L> T1L > T0L