Time-Out (SSTO) – Offset 28 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Time-Out (SSTO) – Offset 28

The Enhanced SSP Time-Out registers have single bit fields that specify the time-out value used to signal a period of inactivity within the Receive FIFO. Note that Writes to reserved bits must be zeroes, and Read value of these bits are undetermined.

Bit Range	Default	Access	Field Name and Description
31:24	0h	NA	RSVD11 (RSVD11) Reserved
23:0	0h	RW	TIMEOUT (TIMEOUT) Timeout Value Is the value that defines the timeout interval for the rcv FIFO. The Interval is given by TIMEOUT/Parallel (Bus) Clock Frequency. When the number of samples in the Receive FIFO is less than rcv FIFO trigger threshold level, and no additional data is received, the Timeout timer will decrement. The time-out timer is reset after a new sample is received. In DMA Mode of operation this value needs to be set when the Rcv FIFO Trigger Threshold is greater than 1 Rcv FIFO Entry (the required Msize (Single Burst) for SSP DMA peripheral transfers) When in PIO mode of operation this value needs to be set when the total transfer size is not an even division of the Rcv FIFO trigger threshold level. Is such a case the TIMEOUT value is calculated to be greater than the time to transfer the FIFO Entry size at the desired Bit Rate. Example Caculation: Tmeout is greater than (RcV FIFO Entry Size) x (1/Serial Bit Rate)/ (1/Bus Clk) = Guard Band x (RcV FIFO Entry Size) x (1/Serial Bit Rate)/ (1/Bus Clk) Example: RcV FIFO Entry = 32 Bits Serial Bit Rate = 1 Mbs Bus Clk = 120 Mhz Gaurd Band = 2x TIMEOUT = (32 (1x10-6))/(8.33 x10-9) = 3840 x 2 = 7680.

Bit Range

Default

Access

Field Name and Description

31:24

RSVD11 (RSVD11)

Reserved

23:0

TIMEOUT (TIMEOUT)

Timeout Value Is the value that defines the timeout interval for the rcv FIFO.
The Interval is given by TIMEOUT/Parallel (Bus) Clock Frequency.
When the number of samples in the Receive FIFO is less than rcv FIFO trigger
threshold level, and no additional data is received, the Timeout timer will
decrement. The time-out timer is reset after a new sample is received. In DMA Mode of operation this value needs to be set when the Rcv FIFO Trigger
Threshold is greater than 1 Rcv FIFO Entry (the required Msize (Single Burst) for
SSP DMA peripheral transfers)
When in PIO mode of operation this value needs to be set when the total transfer
size is not an even division of the Rcv FIFO trigger threshold level.
Is such a case the TIMEOUT value is calculated to be greater than the time to
transfer the FIFO Entry size at the desired Bit Rate.
Example Caculation:
Tmeout is greater than (RcV FIFO Entry Size) x (1/Serial Bit Rate)/ (1/Bus Clk)
= Guard Band x (RcV FIFO Entry Size) x (1/Serial Bit Rate)/ (1/Bus Clk)
Example:
RcV FIFO Entry = 32 Bits
Serial Bit Rate = 1 Mbs
Bus Clk = 120 Mhz
Gaurd Band = 2x
TIMEOUT = (32 (1x10-6))/(8.33 x10-9) = 3840 x 2 = 7680.

Transmit FIFO (SITF)

Data (SSDR) Transmit FIFO (SITF)