Transmit Abort Source (IC_TX_ABRT_SOURCE) – Offset 80 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Transmit Abort Source (IC_TX_ABRT_SOURCE) – Offset 80

This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.

Bit Range	Default	Access	Field Name and Description
31:23	0h	RO	TX_FLUSH_CNT (TX_FLUSH_CNT) This field preserves the TXFLR value prior to the last TX_ABRT event. It is clearedwhenever I2C is disabled. Mode Applicable: Master-Tranmitter
22:21	0h	RO	Reserved (RSVD_IC_TX_ABRT_SOURCE)
20:18	0h	RO	Reserved (RSVD_ABRT_DEVICE_WRITE)
17	0h	RO	Reserved (RSVD_ABRT_SDA_STUCK_AT_LOW)
16	0h	RO	ABRT_USER_ABRT (ABRT_USER_ABRT) This is a master-mode-only bit. Master has detected the user initiated transfer abort (IC_ENABLE[1]) Mode Applicable:Master-Tranmitter
15:13	0h	RO	Reserved
12	0h	RO	ARB_LOST (ARB_LOST) 1: Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the device transmitter has lost arbitration. Mode Applicable: Master Transmitter
11	0h	RO	ABRT_MASTER_DIS (ABRT_MASTER_DIS) 1: User tries to initiate a Master operation with the Master mode disabled. Mode Applicable: Master Transmitter or Receiver
10	0h	RO	ABRT_10B_RD_NORSTRT (ABRT_10B_RD_NORSTRT) 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the master sends a read command in 10-bit addressing mode. Mode Applicable: Master Receiver
9	0h	RO	ABRT_SBYTE_NORSTRT (ABRT_SBYTE_NORSTRT) 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to send a START Byte. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets re-asserted.
8	0h	RO	ABRT_HS_NORSTRT (ABRT_HS_NORSTRT) 1: The restart is disabled (IC_RESTART_EN bit (IC_CON[5]) = 0) and the user is trying to use the master to transfer data in High Speed mode. Mode Applicable: Master Transmitter or Receiver
7	0h	RO	ABRT_SBYTE_ACKDET (ABRT_SBYTE_ACKDET) 1: Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Mode Applicable: Master
6	0h	RO	ABRT_HS_ACKDET (ABRT_HS_ACKDET) 1: Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Mode Applicable: Master
5	0h	RO	ABRT_GCALL_READ (ABRT_GCALL_READ) 1: Controller in master mode sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Mode Applicable: Master Transmitter
4	0h	RO	ABRT_GCALL_NOACK (ABRT_GCALL_NOACK) 1: Controller in master mode sent a General Call and no device on the bus acknowledged the General Call. Mode Applicable: Master Transmitter
3	0h	RO	ABRT_TXDATA_NOACK (ABRT_TXDATA_NOACK) 1: This is a master-mode only bit. Master has received an acknowledgement for the address, but when it sent data byte(s) following the address, it did not receive an acknowledge from the remote device(s). Mode Applicable: Master Transmitter
2	0h	RO	ABRT_10ADDR2_NOACK (ABRT_10ADDR2_NOACK) 1: Master is in 10-bit address mode and the second address byte of the 10-bit address was not acknowledged by any device. Mode Applicable: Master Transmitter or Receiver
1	0h	RO	ABRT_10ADDR1_NOACK (ABRT_10ADDR1_NOACK) 1: Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any device. Mode Applicable: Master Transmitter or Receiver
0	0h	RO	ABRT_7B_ADDR_NOACK (ABRT_7B_ADDR_NOACK) 1: Master is in 7-bit addressing mode and the address sent was not acknowledged by any device. Mode Applicable: Master Transmitter or Receiver