Uncorrectable Error Mask (UEM) – Offset 108 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Uncorrectable Error Mask (UEM) – Offset 108

This is the Uncorrectable Error Mask registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RO	Reserved (RSVD_M) Reserved.
26	0h	RW/P	Poisoned TLP Egress Blocked Mask (PTLPEBM) Mask for Poisoned TLP Egress Blocked error. Register Attribute: Dynamic.
25	0h	RW/P	TLP Prefix Blocked Error Mask (TLPPBEM) Mask for TLP Prefix Blocked Error
24	0h	RW/P	AtomicOp Egress Blocked Mask (AEBM) Mask for AtomicOp Egress Blocked
23	0h	RW/P	MC Blocked TLP Mask (MCBTLPM) Mask bit for MC Blocked TLP error.
22	0h	RW/P	Uncorrectable Internal Error Mask (UIEM) Mask for uncorrectable errors.
21	0h	RW/P	ACS Violation Mask (AVM) Mask for ACS Violation errors.
20	0h	RW/P	Unsupported Request Error Mask (URE) Mask for uncorrectable errors.
19	0h	RW/P	ECRC Error Mask (EE) ECRC error
18	0h	RW/P	Malformed TLP Mask (MT) Mask for malformed TLPs
17	0h	RW/P	Receiver Overflow Mask (RO) Mask for receiver overflows.
16	0h	RW/P	Unexpected Completion Mask (UC) Mask for unexpected completions.
15	0h	RW/P	Completer Abort Mask (CM) Mask for completer abort.
14	0h	RW/P	Completion Timeout Mask (CT) Mask for completion timeouts.
13	0h	RW/P	Flow Control Protocol Error Mask (FCPE) Mask for Flow Control Protocol Error.
12	0h	RW/P	Poisoned TLP Mask (PT) Mask for poisoned TLPs.
11:6	0h	RO	Reserved
5	0h	RW/P	Surprise Down Error Mask (SDE) Surprise Down is not supported.
4	0h	RW/P	Data Link Protocol Error Mask (DLPE) Mask for data link protocol errors.
3:1	0h	RO	Reserved
0	0h	RO	Training Error Mask (TE) Not supported.

Uncorrectable Error Severity (UEV)

Uncorrectable Error Status (UES) Uncorrectable Error Severity (UEV)