Uncorrectable Error Severity (UEV) – Offset 10c - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

Uncorrectable Error Severity (UEV) – Offset 10c

This is the Uncorrectable Error Severity registers. Refer description for each individual field below for more details of the register functionality.

Bit Range	Default	Access	Field Name and Description
31:27	0h	RO	Reserved (RSVD_M) Reserved.
26	0h	RW/P	Poisoned TLP Egress Blocked Severity (PTLPEBS) Severity for Poisoned TLP Egress Blocked error. Register Attribute: Dynamic.
25	0h	RW/P	TLP Prefix Blocked Error Severity (TLPPBES) Severity for TLP Prefix Blocked errors
24	0h	RW/P	AtomicOp Egress Blocked Severity (AEBS) AtomicOp Egress Blocked Severity
23	0h	RW/P	MC Blocked TLP Severity (MCBTLPS) Severity for MC Blocked TLP Error
22	0h	RW/P	Uncorrectable Internal Error Severity (UIES) Severity for Uncorrectable Internal Error
21	0h	RW/P	ACS Violation Severity (AVS) Severity for ACS Violation.
20	0h	RW/P	Unsupported Request Error Severity (URE) Severity for unsupported request reception.
19	0h	RW/P	ECRC Error Severity (EE) ECRC error
18	1h	RW/P	Malformed TLP Severity (MT) Severity for malformed TLP reception.
17	1h	RW/P	Receiver Overflow Severity (RO) Severity for receiver overflow occurrences.
16	0h	RW/P	Unexpected Completion Severity (UC) Severity for unexpected completion reception.
15	0h	RW/P	Completer Abort Severity (CA) Severity for completer abort.
14	0h	RW/P	Completion Timeout Severity (CT) Severity for completion timeout.
13	0h	RW/P	Flow Control Protocol Error Severity (FCPE) Severity for Flow Control Protocol Error.
12	0h	RW/P	Poisoned TLP Severity (PT) Severity for poisoned TLP reception.
11:6	0h	RO	Reserved
5	0h	RW/P	Surprise Down Error Severity (SDE) Surprise Down is not supported.
4	1h	RW/P	Data Link Protocol Error Severity (DLPE) Severity for data link protocol errors.
3:1	0h	RO	Reserved
0	0h	RO	Training Error Severity (TE) TE not supported.

Correctable Error Status (CES)

Uncorrectable Error Mask (UEM) Correctable Error Status (CES)