USB Legacy Keyboard/Mouse Control (ESPI_ULKMC) – Offset 94 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

USB Legacy Keyboard/Mouse Control (ESPI_ULKMC) – Offset 94

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved (RSVD) Reserved
15	0h	RW/1C/V	SMI Caused by End of Pass-through (SMIBYENDPS) Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the Bit 7, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Writing a 1 to this bit will clear the latch.
14	0h	RO	Reserved (RSVD_1) Reserved
13	1h	RW	Reserved (RSVD_2) Reserved
12	0h	RO	Reserved (RSVD_3) Reserved
11	0h	RW/1C/V	SMI Caused by Port 64 Write (TRAPBY64W) Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the Bit 3, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-Through Logic allows specific port 64h Writes to complete without setting this bit.
10	0h	RW/1C/V	SMI Caused by Port 64 Read (TRAPBY64R) Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the Bit 2, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Writing a 1 to this bit will clear the latch.
9	0h	RW/1C/V	SMI Caused by Port 60 Write (TRAPBY60W) Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the Bit 1, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Writing a 1 to this bit will clear the latch. Note that the A20Gate Pass-Through Logic allows specific port 60h Writes to complete without setting this bit.
8	0h	RW/1C/V	SMI Caused by Port 60 Read (TRAPBY60R) Indicates if the event occurred. Note that even if the corresponding enable bit is not set in the Bit 0, then this bit will still be active. It is up to the SMM code to use the enable bit to determine the exact cause of the SMI#. Writing a 1 to this bit will clear the latch.
7	0h	RW	SMI at End of Pass-through Enable (SMIATENDPS) May need to cause SMI at the end of a pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be serviced later.
6	0h	RO/V	Pass Through State (PSTATE) This read-only bit indicates that the state machine is in the middle of an A20GATE pass-through sequence. If software needs to reset this bit, it should set Bit 5 0.
5	0h	RW	A20Gate Pass-Through Enable (A20PASSEN) When enabled, allows A20GATE sequence Pass-Through function (see details below in Section 20.14). When enabled, a specific cycle sequence involving writes to port 60h and port 64h does not result in the setting of the SMI status bits.SMI# will not be generated, even if the various enable bits are set.
4	1h	RW	Reserved (RSVD_4) Reserved
3	0h	RW	SMI on Port 64 Writes Enable (S64WEN) When set, a 1 in bit 11 will cause an SMI event.
2	0h	RW	SMI on Port 64 Reads Enable (S64REN) When set, a 1 in bit 10 will cause an SMI event.
1	0h	RW	SMI on Port 60 Writes Enable (S60WEN) When set, a 1 in bit 9 will cause an SMI event.
0	0h	RW	SMI on Port 60 Reads Enable (S60REN) When set, a 1 in bit 8 will cause an SMI event.