USB2 PHY Power Management Control (USB2_PHY_PMC) – Offset 8164 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Introduction
CNVi WiFi* PCI Configuration
eSPI PCI Configuration
eSPI PCR
GPIO Commumity 0
GPIO Commumity 1
GPIO Commumity 2
GPIO Commumity 3
GPIO Commumity 4
GPIO Commumity 5
GSPI Additional MMIO
GSPI DMA
GSPI MMIO
GSPI PCI Configuration
I2C Additional MMIO
I2C DMA
I2C MMIO
I3C / I2C / UART / GSPI PCR
I3C Additional MMIO
I3C DMA
I3C MMIO
I3C PCI Configuration
IDE-Redirect (IDE-R) PCI Configuration
Integrated GbE PCI Configuration
Integrated Sensor Hub (ISH) MMIO
Integrated Sensor Hub (ISH) PCI Configuration
Intel(R) Management Engine Interface (MEI) MMIO
Intel(R) Management Engine Interface (MEI) PCI Configuration
Intel® High Definition Audio MMIO
Intel® High Definition Audio PCI Configuration
Intergrated GbE MMIO
Keyboard and Text (KT) PCI Configuration
P2SB PCI Configuration
PCIe* PCI Configuration
PMC I/O Based
PMC MMIO
PMC PCI Configuration
PMC SSRAM PCI Configuration
RTC Index
RTC PCR
SATA ABAR
SATA AIDPBA
- AHCI Index Register (INDEX)
- AHCI Data Register (DATA)
SATA Initialization (SIR) Index
SATA MXPBA
- MSI-X Pending Bit Array QW 0 (MXPQW0_DW0)
- MSI-X Pending Bit Array QW 1 (MXPQW0_DW1)
SATA MXTBA
SATA PCI Configuration
SATA Port 0 ABAR
SATA Port 1 ABAR
SATA Port 2 ABAR
SATA Port 3 ABAR
SATA Port 4 ABAR
SATA Port 5 ABAR
SATA Port 6 ABAR
SATA Port 7 ABAR
SMBus MMIO and I/O
SMBus PCI Configuration
SMBus PCR
SMBus TCO I/O
SPI MMIO
SPI PCI Configuration
THC MMIO Common
- Device Idle Control Register (THC_M_CMN_DEVIDLECTRL)
- THC LTR Control Register (THC_M_CMN_LTR_CTRL)
THC MMIO Port
THC PCI Configuration
UART Additional MMIO
UART DMA
UART MMIO
UART PCI Configuration
USB MMIO
USB PCI Configuration
xDCI MMIO Device
xDCI MMIO Global
xDCI PCI Configuration

USB2 PHY Power Management Control (USB2_PHY_PMC) – Offset 8164

USB2 PHY Power Management Control

Bit Range	Default	Access	Field Name and Description
31	0h	RO	Reserved
30:8	0h	RW	Reserved (RSVD) Reserved
7	1h	RW	Enable Command Manager Active Indication for Tx/Rx Bias (EN_CMDM_TXRXB) Enable Command Manager Active indication for Tx/Rx Bias circuit HS Phy PM Policy
6	1h	RW	Enable TTE Tx/Rx Bias (EN_TTE_TXRXB) Enable TTE Active indication for Tx/Rx Bias circuit HS Phy PM Policy
5	1h	RW	Enable IDMA Tx/Rx Bias (EN_IDMA_TXRXB) Enable IDMA Active indication for Tx/Rx Bias circuit HS Phy PM Policy
4	1h	RW	Enable ODMA Tx/Rx Bias (EN_ODMA_TXRXB) Enable ODMA Active indication for Tx/Rx Bias circuit HS Phy PM Policy
3	1h	RW	Enable TRM Tx/Rx Bias (EN_TRM_TXRXB) Enable Transfer Manager Active indication for Tx/Rx Bias circuit HS Phy PM Policy
2	1h	RW	Enable Scheduler Tx/Rx Bias (EN_SCH_TXRXB) Enable Scheduler Active indication for Tx/Rx Bias circuit HS Phy PM Policy
1	0h	RW	Enable Rx Bias ckt disable (EN_RXB_CD) When set enables the Rx bias ckt to be disabled when conditions met (as described by the HS phy PM policy bits)
0	0h	RW	Enable Tx Bias ckt disable (EN_TXB_CD) When set enables the Tx bias ckt to be disabled when conditions met (as described by the HS phy PM policy bits)

XHCI Aux Clock Control Register (XHCI_AUX_CCR)

AUX Power Management Control (AUX_CTRL_REG2) XHCI Aux Clock Control Register (XHCI_AUX_CCR)