USB2 Power Management Control (USB2PMCTRL_REG) – Offset 81c4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

USB2 Power Management Control (USB2PMCTRL_REG) – Offset 81c4

USB2 Power Management Control

Bit Range	Default	Access	Field Name and Description
31:16	0h	RO	Reserved
15	0h	RW	Reserved (RSVD2) Reserved
14	0h	RO	Reserved
13	0h	RW	Bypass Suspend SM (BYPSUSSM) 1: When set, Suspend SM is bypassed and L1/L2 suspendm from the controller goes directly to the PHY 0: When cleared, Suspend SM controls the L1/L2 suspendm to the PHY
12	0h	RW	USB2 HOST PHY UTMI Clock Gate Disable Policy (U2HPUCGDP) This controls the policy for Host PHY UTMI Clock Gating. When Set HOST PHY UTMI Clock Gating is disabled else Host PHY UTMI Clock Gating is enable
11	1h	RW	USB2 PHY SUS Power Gate PORTSC Block Policy (U2PSPGPSCBP) This controls the policy for blocking PORTSC Updates while the USB2 PHY SUS Well is power gated. When set, the controller will block any updates to the PORTSC caused by port status change if the USB2 PHY SUS is power gated. 0 Do not
10:8	1h	RW	USB2 PHY SUS Well Power Gate Entry Hysteresis Count (U2PSPGEHC) This controls the amount of hysteresis time the controller will enforce after detecting the USB2 PHY SUS Power Gate entry condition. 0h 0 clocks 1h 32 clocks 2h 64 clocks 3h 128 clocks 4h 256 clocks 5h 512 clocks 6h 1024 clocks 7h 2048 clocks
7:4	0h	RW	USB2 PHY SUS Power Gate PORTSC Block Policy (U2CLPGLAT) This field represents the worst case latency for the USB2 Common Lane to enter and exit its power gate state. This fields is required to be compared to a ports HIRD/HIRD value for the ports that have allowed L1 to L2 mapping to determine if the Common Lane can be allowed to power off. If the power gate entry/exit latency is greater than the HIRD/HIRDD then the common lane should not be allowed to power gate as this will result in a L1 exit violation. 0h 100 us 1h 200 us 2h 300 us Eh 1500us Fh 1600 us
3:2	2h	RW	USB2 PHY SUS Well Power Gate Policy (U2PSUSPGP) This field controls when to enable the USB2 PHY SUS Well Power Gating when the proper conditions are met. 00 USB2 PHY SUS Power Gating is Disabled. 01 USB2 PHY SUS Power Gating is Enabled in Only D0 and D0i2 (Excludes D0i3 and D3) 10 USB2 PHY SUS Power Gating is Eanabled in only in D0, D0i2 and D0i3 (Excludes D3) 11 USB2 PHY SUS Power Gating is Eanabled in D0/D0i2/D0i3/D3
1:0	0h	RW	Reserved (RSVD1) Reserved