Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) – Offset c4 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

Vendor Specific Component Capabilities for Component 0 (BIOS_SFDP0_VSCC0) – Offset c4

Bit Range	Default	Access	Field Name and Description
31	0h	RO/V	Component Property Parameter Table Valid (CPPTV) This bit is set to a 1 if the Flash Controller detects a valid SFDP Component Property Parameter Table in Component 0. Note: If this bit is set software must not overwrite bits that were initialized by hardware via SFDP discovery.
30	0h	RW/L	Vendor Component Lock (VCL) 0: The lock bit is not set. 1: The Vendor Component Lock bit is set. This register locks itself when set.
29	0h	RW/V/L	64k Erase Valid (EO_64K_VALID) 0: The EO_64k opcode is not valid. 1: The EO_64k opcode is valid.
28	0h	RW/V/L	4k Erase Valid (EO_4K_VALID) 0: The EO_4k opcode is not valid. 1: The EO_4k opcode is valid.
27	0h	RW/L	RPMC Supported (RPMC_SUPPORTED) 0: The device does not support RPMC. 1: The device supports RPMC.
26	0h	RW/V/L	Deep Powerdown Supported (DEEP_PWRDN_SUPPORTED) 0: The device does not support Deep Powerdown. 1: The device supports Deep Powerdown.
25	0h	RW/V/L	Suspend/Resume Supported (SUSPEND_RESUME_SUPPORTED) 1: The device does not support Suspend/Resume. 0: The device supports Suspend/Resume.
24	0h	RW/V/L	Soft Reset Supported (SOFT_RST_SUPPORTED) 0: The device does not support Soft Reset. 1: The device supports Soft Reset.
23:16	0h	RW/V/L	64k Erase Opcode (EO_64K) This register is programmed with the Flash 64k sector erase instruction opcode for component 0. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
15:8	20h	RW/V/L	4k Erase Opcode (EO_4K) This register is programmed with the Flash 4k subsector erase instruction opcode for component 0. Software must program this register if the SFDP table for this component does not show 4 kByte erase capability. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit.
7:5	0h	RW/V/L	Quad Enable Requirements (QER) This field is defined by the JEDEC JESD216A standard for SFDP, reference 2. Information is copied here for reference. The JEDEC standard shall take precedence in the event of a discrepancy. This field describes whether the device contains a Quad Enable (QE) bit used to enable 1-1-4 and 1-4-4 quad read or quad program operations. If QE exists, this field also identifies the bit location and method to set/clear the bit. In this specification, status register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Bits are numbered from 7 to 0, where bit 7 is transferred first on the wire. Note: Industry naming and definitions of these status registers may differ. The user will typically perform a read-modify-write sequence of operations to maintain the state of all other writable status register bits. For example read both status registers, set/clear QE, Write Status with both data bytes. 000b: Device does not have a QE bit. Device detects 1-1-4 and 1-4-4 reads based on instruction. DQ3/HOLD# functions as hold during instruction phase. 001b: QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. Writing only one byte to the status register has the side-effect of clearing status register 2, including the QE bit. The 100b code is used if writing one byte to the status register does not modify status register 2. 010b: QE is bit 6 of status register 1. It is set via Write Status with one data byte where bit 6 is one. It is cleared via Write Status with one data byte where bit 6 is zero. 011b: QE is bit 7 of status register 2. It is set via Write status register 2 instruction 3Eh with one data byte where bit 7 is one. It is cleared via Write status register 2 instruction 3Eh with one data byte where bit 7 is zero. The status register 2 is read using instruction 3Fh. 100b: QE is bit 1 of status register 2. It is set via Write Status with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. In contrast to the 001b code, writing one byte to the status register does not modify status register 2. 101b: QE is bit 1 of the status register 2. Status register 1 is read using Read Status instruction 05h. Status register 2 is read using instruction 35h. QE is set via Write Status instruction 01h with two data bytes where bit 1 of the second byte is one. It is cleared via Write Status with two data bytes where bit 1 of the second byte is zero. Other: Reserved. This register is locked by the Vendor Component Lock (VCL) bit. The flash controller hardware does not use this field. NOTE: This field is only valid for SFDP revision 1.5 and above. Firmware must check the revision prior to acting on the contents of this register.
4	0h	RW/V/L	Write Enable on Write Status (WEWS) 0: 50h is the opcode to enable a status register write. 1: 06h is the opcode to enable a status register write. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit and only issues 06h as a write enable.
3	0h	RW/V/L	Write Status Required (WSR) 0: No requirement to write to the Write Status Register prior to a write. 1: A write is required to the Write Status Register prior to write and erase to remove any protection. This is required for SST components. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit and behaves as if WSR=0. Flash devices that contain a 1 in this field are no longer supported by the flash controller.
2	0h	RW/V/L	Write Granularity (WG) 0 : Reserved. 1 : 64 Byte. This register is locked by the Vendor Component Lock (VCL) bit or the CPPTV bit. Note: Hardware ignores the state of this bit.
1:0	0h	RW/L	Reserved (RSVD) Reserved.