Wake Status (WAKESTS) – Offset e - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

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Wake Status (WAKESTS) – Offset e

This register indicates that a Status Change event has occurred on the link, which usually indicates that either the codec has just come out of reset and is requesting an address, or that a codec is signaling a wake event. Implementation Notes: Because of the legacy implementation of the WAKESTS bits are physically located in the Resume clock domain and it takes time to clock cross the clearing event resulted from SW writing a 1, it is possible that the SW may still read back 1 after clearing the WAKESTS bits, especially if the Resume clock is tied to a slow clock in the SoC, e.g. RTC clock.

Bit Range	Default	Access	Field Name and Description
7:3	0h	RO	Reserved (RSVD1) This is a Reserved Register
2:0	0h	RW/1C/V	SDIN State Change Status Flags (WAKESTS) Flag bits that indicate which SDI signal(s) received a State Change event. The bits are cleared by writing 1s to them.These bits are preserved in Sx state, and may be set during Sx state.

Bit Range

Default

Access

Field Name and Description

7:3

Reserved (RSVD1)

This is a Reserved Register

2:0

RW/1C/V

SDIN State Change Status Flags (WAKESTS)

Flag bits that indicate which SDI signal(s) received a State Change event. The bits are cleared by writing 1s to them.These bits are preserved in Sx state, and may be set during Sx state.

Global Status (GSTS)

Wake Enable (WAKEEN) Global Status (GSTS)