XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) – Offset 8174 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

XHC Latency Tolerance Parameters LTV Control (XLTP_LTV1) – Offset 8174

XHC Latency Tolerance Parameters LTV Control

Bit Range	Default	Access	Field Name and Description
31	0h	RW	Disable scheduler direct transition from IDLE to NO requirement (DIS_SDT_IDL_NR) 0: (default) allow scheduler direct transition from IDLE to NO requirement 1: Disable scheduler direct transition from IDLE to NO requirement
30	0h	RW	XHCI LTR Transition Policy (XLTRTP) (LTR_TRANS_POL) When 0, the LTR messaging state machine transitions through High Med Low Active states assuming enough latency is available for each transition. When 1, LTR messaging state machine transitions from High, Medium, or Low LTR states to Active state upon the Alarm Timer timeout and stays in Active until the next service boundary.
29	0h	RO	Reserved
28	0h	RW	XHCI LTR Active Enable (XLTRAE) (XLTRAE) 0: The Power Scheduler will not request an LTR message on a transition to ACTIVE. 1: The Power Scheduler will request an LTR message on a transition to ACTIVE.
27	0h	RW	Power Scheduler Local Clock Gating Enable (PWRLCGE) (PWRLCGE) 0: Power Scheduler does not use local clock gating 1: Power Scheduler's local clock gating enabled. Note: This functionality is no longer required. This LCG existed previous to the inclusion of Aux clock gating.
26	0h	RO	Reserved
25	1h	RW	Enable USB2 Port L0 LTV based on active async (EN_USB2_LTV_U0_PORT_ASYNC_ACTIVE) 0 - USB2 Port L0 LTV is used regardless of whether there is active async EPs being present or not (Legacy mode) 1 - USB2 LTR L0 LTV is used only when there is active async EPs being present on that port. In the absence of active async EPs on given port, the L0 LTR value is NoRequirement for that port.
24	1h	RW	XHCI LTR Enable (XLTRE) This bit must be set to enable LTV messaging from XHCI to the PMC.
23:12	400h	RW	Periodic Active LTV (PA_LTV) 23:22 Latency Scale 00b : Reserved 01b : Latency Value to be multiplied by 1024 10b : Latency Value to be multiplied by 32,768 11b : Latency Value to be multiplied by 1,048,576 21:12 Latency Value (ns) Defaults to 0 micro seconds
11:0	c01h	RW	USB2 Port L0 LTV (USB2_PL0_LTV) 11:10 Latency Scale 00b : Reserved 01b : Latency Value to be multiplied by 1024 10b : Latency Value to be multiplied by 32,768 11b : Latency Value to be multiplied by 1,048,576 9:0 Latency Value (ns) Defaults to 128 Micro Seconds