XHC System Bus Configuration 1 (XHCC1) – Offset 40 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

hidden text to trigger early load of fonts ПродукцияПродукцияПродукцияПродукция Các sản phẩmCác sản phẩmCác sản phẩmCác sản phẩm المنتجاتالمنتجاتالمنتجاتالمنتجات מוצריםמוצריםמוצריםמוצרים

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

XHC System Bus Configuration 1 (XHCC1) – Offset 40

Bit Range	Default	Access	Field Name and Description
31	0h	RW/1L	Access Control (ACCTRL) This bit is used by BIOS to lock/unlock lockable bits. When set to '1' the write access to bits locked by this bit is disabled (locked state). When set to '0', the write access to bit locked by this bit is enabled (unlocked state). Writable once after platform reset.
30:25	0h	RO	Reserved
24	0h	RW	Master/Target Abort SERR (RMTASERR) When set, it allows the out-of-band error reporting from the xHCI Controller to be reported as SERR# (if SERR# reporting is enabled) and thus set the STS.SSE bit.
23	0h	RW/1C	Unsupported Request Detected (URD) Set the HW when xHCI Controller received an unsupported request posted cycle. Cleared by SW when the bit is written with value of '1'.
22	0h	RW	Unsupported Request Report Enable (URRE) When set this bit allows the URD bit to be reported as SERR# (if SERR# reporting is enabled) and thus set the STS.SSE bit.
21:19	6h	RW	Inactivity Initiated L1 Enable (IIL1E) If programmed to non-zero, it allows L1 power managed to be enabled after the time-out period specified. 000: Disabled 001: 32 bb_cclk 010: 64 bb_cclk 011: 128 bb_cclk 100: 256 bb_cclk 101: 512 bb_cclk 110: 1024 bb_cclk 111: 131072 bb_cclk
18	1h	RW	XHC Initiated L1 Enable (XHCIL1E) If set, allow the XHC initiated L1 power mangement to be enabled.
17	0h	RW	D3 Initiated L1 Enable (D3IL1E) If set, allow PCI device state D3 initiated L1 power managment to be enables.
16:12	0h	RO	Reserved
11	0h	RW	SW Assisted xHC Idle (SWAXHCI) This bit being set will indicate xHC idleness (through SW means), which must be a '1' to allow L1 entry, and subsequently allow backbone clock to be gated. This bit is to be set by Intel xHCI driver after checking that the xHCI Controller will stay in idle state for a significant period of time, e.g. all ports disconnected. This bit can be cleared under the following conditions (see SWAXHCI Policy bits in xHC System Bus Configuration 2 register): SW: SW could write 0 to clear this bit. HW: HW, under policy control, will clear this bit on an MMIO access to the Host Controller. HW: HW, under policy control, will clear this bit when HW exits Idle state.
10:8	1h	RW	L23 to Host Reset Acknowledge Wait Count (L23HRAWC) If programmed to non zero, it allows a wait period after the L23 PHY has shutdown before returning host reset acknowledge to PMC. 000: Disabled 001: 128 bb_cclk 010: 256 bb_cclk 011: 512 bb_cclk 100: 1024 bb_cclk 101: 2048 bb_cclk 110: 4096 bb_cclk 111: 131072 bb_cclk
7:6	3h	RW	Upstream Type Arbiter Grant Count Posted (UTAGCP) Grant count for IOSF upstream L2 request type arbiter for posted type
5:4	3h	RW	Upstream Type Arbiter Grant Count Non Posted (UDAGCNP) Grant count for IOSF upstream L2 type arbiter for non-posted type
3:2	3h	RW	Upstream Type Arbiter Grant Count Completion (UDAGCCP) (UDAGCCP) Grant count for IOSF upstream L2 type arbiter for completion type
1:0	1h	RW	Upstream Device Arbiter Grant Count (UDAGC) (UDAGC) Grant count for IOSF upstream L1 device arbiter