XHC System Bus Configuration 2 (XHCC2) – Offset 44 - 001 - ID:834576 | Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

Intel® 800 Series Chipset Family Platform Controller Hub (PCH), Volume 2

ID	Date	Version	Classification
834576	10/10/2024	001	Public

XHC System Bus Configuration 2 (XHCC2) – Offset 44

Bit Range	Default	Access	Field Name and Description
31	0h	RW	OC Configuration Done (OCCFGDONE) This bit is used by BIOS to prevent spurious switching during OC configuration. It must be set by BIOS after configuration of the OC mapping bits is complete. Once this bit is set, OC mapping shall not be changed by SW.
30	0h	RW	Enable Relaxed Ordering (RO_EN) This bit is used to assert Relaxed Ordering bit
29:28	0h	RW	MMIO Back to Back Rd/Wr Delay Count (RW_DLY_CNT) This field controls the delay in PRIM_CLK clocks applied to the delay inserted between the MMIO Rd/Wr or Wr/Wr back to back scenarios if enabled via XHCC2[11:10] 0x0 - 64 clocks 0x1 - 128 clocks 0x2 - 256 clocks 0x3 - N/A
27:26	0h	RO	Reserved
25	0h	RW	DMA Request Boundary Crossing Control (DREQBCC) This bit controls the boundary crossing limit of each Read/Write Request. 0: 4KB 1: 64B
24:22	0h	RW	IDMA Write Request Size Control (WRREQSZCTRL) Write Request Size Control: This bit controls the maximum size of each Write Request. 000: 128B 001: 256B 011 - 110: Reserved 111: 64B
21	1h	RW	XHC Upstream Read Relaxed Ordering Enable (XHCUPRDROE) Setting this to 1 disable downstream completion resource checking and allow \t\t\t upstream NP ready beyonf Non-posed pre-allocation limit set by bits 20:14
20:14	7fh	RW	Upstream Non-Posted Pre-Allocation (UNPPA) This field reserves data sizes, in 64 byte chunks, of the downstream completion resource. This value is zero based. 000000 - 111111: Pre-allocate 64 bytes - 4096 bytes If set greater than the default allows over-allocation If set less than default allows under-allocation Only allowed to be programmed when BME = 0 and no outstanding downstream completion
13:12	0h	RW	SW Assisted xHC Idle Policy (SWAXHCIP) Note: Irrespective of the setting of this field, SW write of 0 to SWAXHCI will clear the bit. 00b (default): xHC HW clears SWAXHCI bit upon: MMIO access to Host Controller OR xHC HW exits Idle state 01b: xHC HW does not autonomously clear SWAXHCI bit. The bit could be cleared only by SW. 10b: xHC HW clears SWAXHCI upon MMIO acces to Host Controller. xHC HW exit from Idle state will not clear SWAXHCI. 11b: Reserved
11	1h	RW	MMIO Read After MMIO Write Delay Disable (RAWDD) This field controls delay on MMIO Read after MMIO Write. 0b (Default): Delay MMIO Read after MMIO Write 1b: Do not delay MMIO Read after MMIO Write Note that this delay applies after the second of the two DW writes in the case where the IOSF Gasket splits a QW write into two single DW writes to the IP.
10	0h	RW	MMIO Write After MMIO Write Delay Enable (WAWDE) This field controls delay on MMIO Write after previous MMIO Write. 0b (Default): Do not delay MMIO Write after previous MMIO Write 1b: Delay MMIO Write after previous MMIO Write Note that the delay count does not apply on the second of the two DW writes that are generated by IOSF Gasket when it splits a QW write into two. In other words, the second of the two DW writes could happen without any delay with respect to the first DW write. This choice is being made for ease of Electronic Change Order. The delay count, in this case, will apply after the second of the two DW writes.
9:8	2h	RW	SW Assisted Cx Inhibit (SWACXIHB) This field controls how the DMI L1 inhibit signal from USB3 to PMC will behave. 00: Never inhibit Cx 01: Inhibit Cx when Isochronous Endpoint is active (PPT Behavior) 10: Inhibit Cx when Periodic Active 11: Always inhibit Cx
7:6	2h	RW	SW Assisted DMI L1 Inhibit (SWADMIL1IHB) This field controls how the DMI L1 inhibit signal from USB3 to DMI will behave. 00: Never inhibit DMI L1. 01: Inhibit DMI L1 when Isochronous Endpoint is active (PPT Behavior). 10: Inhibit DMI L1 when Priodic Active 11: Inhibit DMI L1 if XHCC1.SWAXHCI = 0.
5:3	1h	RW	L1 Force P2 Clock Gating Wait Count (L1FP2CGWC) If programmed to non zero, it allows L1 force P2 gating off the clock to be delayed after the time-out period specified. If wake up event is detected before the time-out, pclk remains alive and trigger L1 exit as though CPU host is causing the wake, 000: Disabled 001: 128 bb_cclk 010: 256 bb_cclk 011: 512 bb_cclk 100: 1024 bb_cclk 101: 2048 bb_cclk 110: 4096 bb_cclk 111: 131072 bb_cclk
2:0	0h	RW	Read Request Size Control (RDREQSZCTRL) Read Request Size Control: This bit controls the maximum size of each Read Request. 000: 128B 001: 256B 010: 512B 011 - 110: Reserved 111: 64B