Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
Base Address (PM_BAR) – Offset 10
This is the base address of the 256kB MMIO space for the Punit Crashlog SRAM
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 63:39 | 0h | RO | Reserved |
| 38:15 | 0h | RW | PMBAR Address (PMBAR) This field corresponds to bits 38 to 15 of the base address PMBAR address space. |
| 14:4 | 0h | RO | Address Mask (ADDRESS_MASK) Hardwired to 0s to indicate at least 32KB address range. |
| 3 | 0h | RO | BAR is Prefetchable (PREFETCHABLE) Value of 0 indicates the BAR cannot be prefetched. |
| 2:1 | 2h | RO | Address Range (ADDRESS_RANGE) Address Range: Value of 0x2 indicates that the BAR is located anywhere system memory space (i.e. 64-bit addressing). |
| 0 | 0h | RO | Memory Space Indicator (SPACE_TYPE) Value of 0 indicates the BAR is located in memory space. |