31:24

6h

RW

Write Latency - CWL/WL (tCWL)

Holds DDR timing parameter tCWL (sometimes referred to as tWCL).
Write command to data delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-64 (maximum is for 1N mode)
For LPDDR4 the minimum supported value is 4.

23

0h

RO

Reserved

22:16

5h

RW

Read Latency - CL/RL (tCL)

Holds DDR timing parameter tCL.
Read command to data delay in tCK (WCK for LPDDR5) cycles.
Supported range is 4-72.

15:6

0h

RO

Reserved

5:0

8h

RW

tCCD 32 byte CAS delta (tccd_​32_​byte_​cas_​delta)

For LPDDR technologies, MC will subtract this value from the following timing turnarounds when a 32 byte Rd/Wr CAS is scheduled:

tc_​rdrd_​0_​0_​0_​mchbar
tc_​rdwr_​0_​0_​0_​mchbar
tc_​wrrd_​0_​0_​0_​mchbar
tc_​wrwr_​0_​0_​0_​mchbar
wck_​config_​0_​0_​0_​mchbar.{rd_​wck_​async_​gap,wr_​wck_​async_​gap}

This field should be programmed in tCK clocks for LPDDR4. A value between 0 and 8 is supported.
This field should be programmed in WCK clocks for LPDDR5. In 16 bank mode the value must be 8. In 4 bank group, 4 bank mode the value must be 16.
In 8 bank mode the value must be 0. Note that tRDRD_​dg and tWRWR_​dg are excluded from this adjustment in 4 bank group, 4 bank mode and the same turnaround values will be used for both 64B and 32B CAS commands.

For DDR5, this field should be programmed to the delta between tCCD_​L_​WR and tCCD_​L_​WR2 in tCK clocks.