Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
D0i3 And Power Control Enable (D0I3_MAX_POW_LAT_PG_CONFIG) – Offset a0
D0idle_Max_Power_On_Latency register set at boot and Power control enable register to enable communication with the PGCB block below the Bridge
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:22 | 0h | RO | Reserved |
| 21 | 0h | RW/P | Hardware Autonomous Enable (HAE) If 1, then hardware may request power gating whenever it has reached an idle condition. |
| 20 | 0h | RO | Reserved |
| 19 | 0h | RW/P | Sleep Enable (SLEEP_EN) 1: The function may assert Sleep during power gating. |
| 18 | 0h | RW/P | D3-Hot Enable (D3HEN) If 1, then function will power gate when idle and the PMCSR [1:0] register in the function = b11 (D3). |
| 17 | 0h | RW/P | Device Idle Enable (DEVIDLEN) If 1, then the function will power gate when idle and the DevIdle register (DevIdleC [2] = 1) is set. |
| 16 | 0h | RW/P | PMC Request Enable (PMCRE) If this bit is set to 1, the function will power gate when idle and pmc_(ip)_sw_pg_req_b =0. |
| 15:13 | 0h | RO | Reserved |
| 12:10 | 2h | RW/O/P | Power Latency Scale (POW_LAT_SCALE) Power On Latency Scale |
| 9:0 | 0h | RW/O/P | Power Latency Value (POW_LAT_VALUE) Power On Latency value |