Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
Device 2 Mirror of Protected Audio Video Path Control (PAVPC0_0_2_0_PCI) – Offset f0
Device 2 Mirror of Protected Audio Video Control.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:20 | 0h | RO/V | WOPCM Base LSB (WOPCMBASE_LSB) Base value programmed (from Top of Stolen Memory). The programmed value must be consistent with the WOPCM Size programming. |
| 19:13 | 0h | RO | Reserved |
| 12:11 | 1h | RO/V | SA MEDIA WOPCM SIZE (SAM_WOPCMSIZE) This register determines the WOPCM size. The programmed value must be consistent with the WOPCM base programming. |
| 10:7 | 0h | RO | Reserved |
| 6 | 0h | RO/V | ASMF Method Enable (ASMFEN) 0: Disable ASMF |
| 5 | 0h | RO/V | VDBOX RESET COUNTER CHECKIN DISABLE (vdboxResetCounterCheckinDisable) vdbox Reset Counter Checkin Disable. 0: Enable feature: KCR will check in encryption counters from ECR on engine reset irrespective of Reset DCN feature state. 1: Disable feature: KCR will check in encryption counters from ECR on engine reset only when Reset DCN is enabled. |
| 4 | 0h | RO/V | Override Terminate Attack (OVTATTACK) Override of unsolicited connection state attack and terminate |
| 3 | 0h | RO/V | Heavy Mode Select (HVYMODSEL) Heavy/light encryption mode select 0: Surface encryption is disabled - Light mode 1: Surface encryption is enabled |
| 2 | 0h | RO/V | Lock Bit (LOCK) BIOS will set this bit with bit 0 and/or bit 1. |
| 1 | 0h | RO/V | PAVP Enable (PAVPE) 0: PAVP functionality disabled |
| 0 | 0h | RO/V | PCM Enable (PCME) Protected content memory enable. |