31:22

0h

RO

Reserved

21

0h

RO/V

Transaction Pending (DEVICESTS)

When Set, this bit indicates that the Function has issued Non-Posted Requests that have not been completed.
A Function reports this bit is cleared only when all outstanding Non-Posted Requests have completed or have been terminated by the Completion Timeout mechanism.
This bit must also be cleared upon the completion of an FLR.

20

0h

RO

AUX Power Detected (Relax_​Ord_​En)

Not used, always 0.

19

0h

RW/1C/V

Unsupported Request Detected (UR_​Req_​Det)

Set when IUNIT recieve P/NP transaction which is UR.

18:16

0h

RO

Misc Errors (DEVICECTL_​MISC_​STS)

Bits 2:0: Various error detected bits.
The Root Complex Integrated Endpoint does not use the PCI Express error reporting mechanism.
Always return 0.

15

0h

RW

Initiate Function Level Reset (INIT_​FLR)

A write of 1b initiates Function Level Reset to the Function.
The value read by software from this bit is always 0b.

14:0

0h

RO

Misc Device Control (DEVICECTL_​MISC_​CTRL)

The only bit set reflect Unsupported-Request-Reporting Enable