Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
Device Idle Duration Override (DEVICE_IDLE_DURATION_OVERRIDE_0_0_0_MCHBAR_PCU) – Offset 59c8
MDID override register to be used by OS or software for debug purposes.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31 | 0h | RO | Reserved |
| 30 | 0h | RW | Force MDID Override (FORCE_MDID_OVERRIDE) When this bit is set, and bit 1 (the valid bit) is set, the value specified in this field will be used for MDID purposes. If this bit is clear, and bit 1 (the valid bit) is set, this value should be consumed along with the other MDID registers to determine which value is expiring next and reporting that value. |
| 29 | 0h | RW | Disable MDID Evaluation (DISABLE_MDID_EVALUATION) Send a value of disabled to the PCH for the MDID field. |
| 28:8 | 0h | RW | Next Device Activity (NEXT_DEVICE_ACTIVITY) These are in 1us increments and can report a maximum value of approximately 2 seconds |
| 7 | 0h | RW | Interrupt or Memory (IM) 0: Interrupt. This is a hint for the idle duration time to the next interrupt. |
| 6 | 0h | RW | Opportunistic or Deterministic (OD) 0: Opportunistic. This is an opportunistic hint as suggested by the sub-system. |
| 5:2 | 0h | RO | Reserved |
| 1 | 0h | RW | (VALID) 0: This Idle Duration Override CSR is not valid |
| 0 | 0h | RO | Reserved |