Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
ECC Error Log 0 (ECCERRLOG0_0_0_0_MCHBAR) – Offset e048
This register logs ECC error information.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:29 | 0h | RO/V/P | Error Bank (ERRBANK) This field holds the Bank Address of the read transaction that had the ECC error. |
| 28:27 | 0h | RO/V/P | Error Rank (ERRRANK) This field holds the Rank ID of the read transaction that had the ECC error. |
| 26:24 | 0h | RO/V/P | Error Chunk (ERRCHUNK) Holds the chunk number of the error stored in the register. |
| 23:16 | 0h | RO/V/P | Error Syndrome (ERRSYND) This field contains the error syndrome. A value of 0xFF indicates that the error is due to poisoning. |
| 15:4 | 0h | RO | Reserved |
| 3 | 0h | RW/1C/V/P | Multiple-bit Error Overflow (MERR_OVERFLOW) This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer after one has already been logged in MERRSTS field. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared. |
| 2 | 0h | RW/1C/V/P | Multiple-bit Error Status (MERRSTS) This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer. |
| 1 | 0h | RW/1C/V/P | Correctable Error Overflow (CERR_OVERFLOW) This bit is set when a correctable single-bit error occurs on a memory read data transfer after one has already been logged in CERRSTS field. This bit is cleared when the corresponding bit in 0.0.0.PCI.ERRSTS is cleared. |
| 0 | 0h | RW/1C/V/P | Correctable Error Status (CERRSTS) This bit is set when a correctable single-bit error occurs on a memory read data transfer. |