63

0h

RW/1C/V/P

Uncorrectable (Multiple-bit) Error Status (MERRSTS)

This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked until this bit is cleared. This field can be cleared by writing 1.

62

0h

RW/1C/V/P

Correctable Error Status (CERRSTS)

This bit is set when a correctable single-bit error occurs on a memory read data transfer. When this bit is set, the address that caused the error and the error syndrome are also logged and they are locked to further single bit errors, until this bit is cleared. But, a multiple bit error that occurs after this bit is set will over-write the address/error syndrome info. Writing 1 to this field by software will clear this field.

61:46

0h

RO/V/P

ECC Error Syndrome (ERRSYND)

Error Syndrome that is associated with the failing Cache Line

45:39

0h

RO

Reserved

38:5

0h

RO/V/P

Error Address (ERRADD)

CMI address of the address block of main memory of which an error (single bit or multi-bit error) has occurred.

4

0h

RO/V/P

Multiple Bit Error Overflow (MERR_​OVERFLOW)

This bit is set when an uncorrectable multiple-bit error occurs on a memory read data transfer and the MERRSTS bit is already set, indicating that more than one error has occurred. Hardware clears this bit when MERRSTS is cleared by SB write.

3

0h

RO/V/P

Correctable Error Overflow (CERR_​OVERFLOW)

This bit is set when a correctable single-bit error occurs on a memory read data transfer and the MERRSTS bit is already set, indicating that more than one error has occurred. Hardware clears this bit when CERRSTS is cleared by SB write.

2:0

0h

RO

Reserved