Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) – Offset 10 - 001 - ID:844345 | Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers

Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers

ID	Date	Version	Classification
844345	01/29/2025	001	Public

Graphics Translation Table Memory Mapped Range Address (GTTMMADR0_0_2_0_PCI) – Offset 10

This register requests allocation for the combined Graphics Translation Table Modification Range and Memory Mapped Range. The range requires 16 MB combined for MMIO and Global GTT aperture, with 2MB of that used by MMIO, 6MB reserved, and 8MB used by GTT. GTTADR will begin at (GTTMMADR + 8 MB) while the MMIO base address will be the same as GTTMMADR. The region between (GTTMMADR + 2MB) - (GTTMMADR + 8MB) is reserved. For the Global GTT, this range is defined as a memory BAR in graphics device configuration space. It is an alias into which software is required to write Page Table Entry values (PTEs). Software may read PTE values from the global Graphics Translation Table (GTT). PTEs cannot be written directly into the global GTT memory area. The device snoops writes to this region in order to invalidate any cached translations within the various TLBs implemented on-chip. The allocation is for 16MB and the base address is defined by bits [38:24].

Bit Range	Default	Access	Field Name and Description
31:26	0h	RW/V	Memory Base Address (MBA_0) Set by the OS, these bits correspond to address signals [63:24].
25	0h	RW/V	MEMORY BASE ADDRESS TILE 1 (MBAT_1) Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0. On an FLR, bits 25:24 should be cleared to defaults (2'b0)
24	0h	RW/V	MEMORY BASE ADDRESS TILE 0 (MBAT_0) Set by the OS, these bits correspond to address signals [25:24]. The accessibility of these registers is governed by the tile count. If 1 tile, then these are R/W. If 2 tiles, then bit 24 is RO=0, bit 25 is R/W. If 4 tiles, then bits 25:24 are RO=0. On an FLR, bits 25:24 should be cleared to defaults (2'b0)
23:4	0h	RO	Address Mask (ADM) Hardwired to 0s to indicate at least 16MB address range.
3	1h	RO/V	Prefetchable Memory (PREFMEM) Default to 1 to indicate prefetchable.
2:1	2h	RO	Memory Type (MEMTYP) Hardwired to 2h to indicate 64 bit base address.
0	0h	RO	Memory I/O Space (MIOS) Hardwired to 0 to indicate memory space.