Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
IBECC Memory Initialization Control (IBECC_MEMORY_INIT_CONTROL) – Offset d630
IBECC hardware memory initialization control.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31 | 0h | RW/V | Initialize All Ranges (INIT_ALL_RANGES) When set, IBECC starts initialization of all enabled ranges starting from range 0 to range 7 and will clear the bit once all ranges are initialized. |
| 30:8 | 0h | RO | RSVD (RSVD) Reserved |
| 7 | 0h | RW/V | Initialize Range 7 (INIT_RANGE_7) When set, IBECC starts initialization of range 7 and will clear the bit once done. |
| 6 | 0h | RW/V | Initialize Range 6 (INIT_RANGE_6) When set, IBECC starts initialization of range 6 and will clear the bit once done. |
| 5 | 0h | RW/V | Initialize Range 5 (INIT_RANGE_5) When set, IBECC starts initialization of range 5 and will clear the bit once done. |
| 4 | 0h | RW/V | Initialize Range 4 (INIT_RANGE_4) When set, IBECC starts initialization of range 4 and will clear the bit once done. |
| 3 | 0h | RW/V | Initialize Range 3 (INIT_RANGE_3) When set, IBECC starts initialization of range 3 and will clear the bit once done. |
| 2 | 0h | RW/V | Initialize Range 2 (INIT_RANGE_2) When set, IBECC starts initialization of range 2 and will clear the bit once done. |
| 1 | 0h | RW/V | Initialize Range 1 (INIT_RANGE_1) When set, IBECC starts initialization of range 1 and will clear the bit once done. |
| 0 | 0h | RW/V | Initialize Range 0 (INIT_RANGE_0) When set, IBECC starts initialization of range 0 and will clear the bit once done. |