31:25

0h

RO

Reserved

24

0h

RW

Decoder Extended Bank Hashing (decoder_​ebh)

Enable address decoder Extended bank hashing.
Bit 0: Enable XaB
Bit 1: Enable XbB

23:21

0h

RW

BG2 Hashing arbiter (bg2hash)

Chooses which address bit will XOR with BG[2]
0x0: disable (XOR with 0, keeps default DRAM decoding values)
0x1: A[6]
0x2: A[7]
0x3: A[8]
0x4: A[9]
0x5: A[10]
0x6: A[11] (DDR5 Only)
0x7: reserved
Note: In LPDDR4 and LPDDR5 8B mode, BG0H applies to Bank Bits instead.
Note: BGHash XOR is not affected by EIM.

20:18

0h

RW

BG1 Hashing arbiter (bg1hash)

Chooses which address bit will XOR with BG[1]
0x0: disable (XOR with 0, keeps default DRAM decoding values)
0x1: A[6]
0x2: A[7]
0x3: A[8]
0x4: A[9]
0x5: A[10]
0x6: A[11] (DDR5 Only)
0x7: reserved
Note: In LPDDR4 and LPDDR5 8B mode, BG0H applies to Bank Bits instead.
Note: BGHash XOR is not affected by EIM.

17:15

0h

RW

BG0 Hashing arbiter (bg0hash)

Chooses which address bit will XOR with BG[0]
0x0: disable (XOR with 0, keeps default DRAM decoding values)
0x1: A[6]
0x2: A[7]
0x3: A[8]
0x4: A[9]
0x5: A[10]
0x6: A[11] (DDR5 Only)
0x7: reserved
Note: In LPDDR4 and LPDDR5 8B mode, BG0H applies to Bank Bits instead.
Note: BGH XOR is not affected by EIM.

14

0h

RO

Reserved

13:12

0h

RW

ECC Channel Configuration (ecc)

0: No ECC active in the channel.
1: ECC is active in IO, ECC logic is not active.
2: ECC is disabled in IO, but ECC logic is enabled.
3: ECC active in both IO and ECC logic.
Notes:

• This field must be programmed identically for all populated channels.
  
• In a system with ECC this field must be programmed to 1 during training and then 3 before transitioning from training mode to Normal mode.

11:9

0h

RO

Reserved

8

0h

RW

Enhanced Interleaving Mode (eim)

0b: Disabled
1b: Enabled

7:1

0h

RO

Reserved

0

0h

RW

DIMM L Mapping (dimm_​l_​map)

Virtual DIMM L mapping to physical DIMM
0b: DIMM0
1b: DIMM1