Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
IPU BAR LOW (ISPMMADR_LOW) – Offset 10
Low Part of Base Address Register
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:24 | 0h | RW | Base Address (BASE_ADDR) Set by the OS, these bits correspond to address signals (31:24). |
| 23:4 | 0h | RO | Address Mask (ADDR_MASK) Hardwired to 0s to indicate at least 16MB address range. |
| 3 | 0h | RO | Prefetchable Memory (PREFETCHABLE) Hardwired to 0 to prevent prefetching. |
| 2:1 | 2h | RO | Memory Type (TYPE) 2h indicates 64 bit wide addressing. |
| 0 | 0h | RO | Message Space (MESSAGE_SPACE) 0h indicates memory space. |