31:24

0h

RO

Port Number (PORTNUM)

PCIe port number for the given PCIe link.

23

0h

RO

Reserved

22

1h

RO

ASPM Optionality Compliance (ASPMOCOMP)

This bit must be set to 1b in all Functions. Software is permitted to use the value of this bit to help determine whether to enable ASPM or whether to run ASPM compliance tests

21

0h

RO

Link Bandwith Notification Capability (LINKBWNOT)

This field is reserved for PCIe endpoints.

20

0h

RO

Link Active Report Capability (LARC)

This bit must be 1b if component supports optional cap of reported DL_​Active state.

19

0h

RO

Surprise Down Report Cpability (SDRC)

Set if optional capability of detecting and reporting a surprise down error condition.

18

0h

RO

Clock PM (CLKPM)

This bit must be hardwired to 0b.

17:15

0h

RO

L1 Exit Latency (L1EXIT)

This field indicates the L1 exit latency of the given PCIe link. The value reported indicates the length of time this port required to complete transtion from ASPM L1 to L0. 000b=less than 1us.

14:12

0h

RO

L0S Exit Latency (L0SEXIT)

This field indicates the L0s exit latency fo the given PCIe link. The value reported indicates the length of time this port requires to complete transition from L0s to L0. 000b=less than 64ns.

11:10

3h

RO

Active State PM (ASPM)

This field indicates the level of ASPM supported on the given PCIe Link. Hardwired to 11 to indicate L0s and L1 supported.

9:4

1h

RO

Maximum Link Width (MAXLINKWID)

Maximum Link Width Per IOSF spec recommendation, report x1. Encoding is 00 0001b (x1 width).

3:0

1h

RO

Maximum Link Speed (MAXLINKSPD)

Max Link Speed Per IOSF Spec, report Gen1. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the maximum Link speed. The encoding is 0001b.