Intel® Core™ Ultra 200H and 200U Series Processors CFG and MEM Registers
| ID | Date | Version | Classification |
|---|---|---|---|
| 844345 | 01/29/2025 | 001 | Public |
Local Memory Bar (LMEMBAR1_0_2_0_PCI) – Offset 1c
The Local Memory Bar is used by S/W to access Gfx Gdie local memory.
| Bit Range | Default | Access | Field Name and Description |
|---|---|---|---|
| 31:7 | 0h | RW/V | MEMORY BASE ADDRESS (MBA) Set by the OS, these bits correspond to address signals [63:39]. |
| 6 | 0h | RW/V | 512GB ADDRESS MASK (ADMSK512GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 512GB |
| 5 | 0h | RW/V | 256GB ADDRESS MASK (ADMSK256GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 256GB |
| 4 | 0h | RW/V | 128GB ADDRESS MASK (ADMSK128GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 128GB |
| 3 | 0h | RW/V | 64GB ADDRESS MASK (ADMSK64GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 64GB |
| 2 | 0h | RW/V | 32 GB ADDRESS MASK (ADMSK32GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 32GB |
| 1 | 0h | RW/V | 16 GB ADDRESS MASK (ADMSK16GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 16GB |
| 0 | 0h | RW/V | 8 GB ADDRESS MASK (ADMSK8GB) This bit is either part of the Memory Base Address (R/W) or part of Address Mask (RO) depending on the value of PF_RESZ_CTRL.PFBARSIZE. RO and force to zero when PF_RESZ_CTRL.PFBARSIZE >= 8GB |